# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 64 Issue 6 • June 2017

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## Filter Results

Displaying Results 1 - 25 of 34

Publication Year: 2017, Page(s): C1
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
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• ### 94-GHz CMOS Power Amplifiers Using Miniature Dual Y-Shaped Combiner With RL Load

Publication Year: 2017, Page(s):1285 - 1298
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This paper reports two four-way 94-GHz power amplifiers (PAs) for radar sensors in 90-nm CMOS technology. The first PA (PA1) comprises a two-stage common-source (CS) cascaded input stage with wideband π -match input, interstage and output networks, followed by a two-way CS gain stage using Y-shaped divider and combiner, and a four-way CS output stage using dual Y-shaped divider and combiner... View full abstract»

• ### Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder

Publication Year: 2017, Page(s):1299 - 1307
Cited by:  Papers (1)
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An exponentially scaling C-2C switched-capacitor (SC) ladder is proposed for millimeter-wave digitally controlled oscillators (DCOs) to achieve high-frequency resolution with small chip area. The 65-nm-CMOS DCO prototype measures a frequency resolution of 4 Hz over a frequency range of 14.2%, from 54.79 to 63.16 GHz, with a phase noise at 1-MHz frequency offset of -90.7 to -94.1 dBc/Hz while consu... View full abstract»

• ### A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

Publication Year: 2017, Page(s):1308 - 1317
Cited by:  Papers (4)
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This paper presents a precision bandgap reference with an innovative adjusted-temperature-curvature compensation circuit that obtains a good temperature coefficient (TC) over a wide temperature range. The proposed compensation circuit for enhancing the voltage accuracy of the bandgap reference combines an addition circuit, subtraction circuit, and current mirror to achieve an adjusted piecewise li... View full abstract»

• ### A Power-Efficient Reconfigurable Output-Capacitor-Less Low-Drop-Out Regulator for Low-Power Analog Sensing Front-End

Publication Year: 2017, Page(s):1318 - 1327
Cited by:  Papers (1)
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A power efficient reconfigurable output-capacitorless (OCL) low-drop-out (LDO) voltage regulator for low-power analog sensing front-end is proposed in this paper. This LDO consists of a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. The error amplifier adopts a class-AB input differential ... View full abstract»

• ### A High-Voltage Closed-Loop SC Interface for a ± 50 g Capacitive Micro-Accelerometer With 112.4 dB Dynamic Range

Publication Year: 2017, Page(s):1328 - 1341
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A low-noise high-linearity switched capacitor interface implemented in a 0.35$mu text {m}$ 3.3 V/15 V CMOS process is presented in this paper for a ±50g capacitive micro-accelerometer. The sensing element is enclosed in an optimized closed loop with proportional-integral compensation, improving the linearity significantly. In order to suppress the flicker noise of the front-end at the lowes... View full abstract»

• ### A Nonlinear Switched State-Space Model for Capacitive RF DACs

Publication Year: 2017, Page(s):1342 - 1353
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This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal-oxide-semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current-voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compare... View full abstract»

• ### A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS

Publication Year: 2017, Page(s):1354 - 1367
Cited by:  Papers (1)
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A Nyquist voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) architecture is proposed for ac-coupled systems that are commonly used in high-speed wireline and wireless communications. The proposed ADC utilizes a built-in high-pass filter as an analog differentiator, replacing the digital differentiator in conventional oversampling VCO-based ADCs. As a result, it avoids qua... View full abstract»

• ### A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing

Publication Year: 2017, Page(s):1368 - 1379
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A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode d... View full abstract»

• ### Ramp Noise Projection in CMOS Image Sensor Single-Slope ADCs

Publication Year: 2017, Page(s):1380 - 1389
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Noise analysis of the ramp reference voltage and its projection at the output of a conventional single-slope ramp analog-to-digital converter (ADC) is presented. This paper gives insight on the reference voltage noise origins during the continuous-time ramping phase of column-parallel CMOS image sensor ADCs, as well as its effect on the final ADC output noise. Theoretical modeling of an occurring ... View full abstract»

• ### Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers

Publication Year: 2017, Page(s):1390 - 1399
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The output signal of a digital delta-sigma modulator (DDSM) with a constant input may has a small fundamental period and therefore its spectrum may be characterized by a small number of strong periodic tones. Pseudorandom dither can be used to break up the tones, but it is indistinguishable from signal. The dither signal can be masked by using short sequence lengths but this may result in ineffect... View full abstract»

• ### A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds

Publication Year: 2017, Page(s):1400 - 1408
Cited by:  Papers (1)
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This paper presents an analog-to-digital (A-to-D) conversion algorithm to break through the speed limitation of the analog-to-digital converters in advanced technology. The proposed A-to-D conversion algorithm utilizes the benefits of the speed-up techniques of sub-radix and multi-bit per cycle. We model the Vin - Vq transfer curves into linear equations with hardware-like pa... View full abstract»

• ### Improving Digital-to-Analog Converter Linearity by Large High-Frequency Dithering

Publication Year: 2017, Page(s):1409 - 1420
Cited by:  Papers (2)
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A new method for reducing harmonic distortion due to element mismatch in digital-to-analog converters is described. This is achieved by using a large high-frequency periodic dither. The reduction in nonlinearity is due to the smoothing effect this dither has on the nonlinearity, which is only dependent on the amplitude distribution function of the dither. Since the high-frequency dither is unwante... View full abstract»

• ### Spike-Based Readout of POSFET Tactile Sensors

Publication Year: 2017, Page(s):1421 - 1431
Cited by:  Papers (1)
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We present a low-power compact circuit for the event-driven readout of tactile sensors. The taxel is based on the POSFET device, a sensotronic unit where a piezo-electric material is deposited on the gate of a transistor, integrated with a Leaky-Integrate and Fire neuron circuit. This device encodes the applied force with trains of digital pulses, using the asynchronous Address Event Representatio... View full abstract»

• ### A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

Publication Year: 2017, Page(s):1432 - 1443
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This paper presents a 2.5D integrated microprocessor die, memory die, and accelerator die with 2.5D silicon interposer I/Os. The use of such 2.5D silicon interposer I/Os provide a scalable interconnection for core-core (up to 32 cores), core-memory (4× storage capacity) and core-accelerator (4.4× speedup in H.264 decoder). The 2.5D integrated chip was implemented in GF 65 nm process ... View full abstract»

• ### Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM

Publication Year: 2017, Page(s):1444 - 1455
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Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing ... View full abstract»

• ### 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches

Publication Year: 2017, Page(s):1456 - 1467
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In this paper, we propose a reconfigurable (RC) fast Fourier transform (FFT) design in a systematic design scheme. The RC design bricks are mainly proposed to arbitrarily concatenate to support FFT-point required. Meanwhile, we show three developed design techniques, including six-type RC processing element, systematic first-in first-out reuse arrangement, and section-based twiddle factor generato... View full abstract»

• ### Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm

Publication Year: 2017, Page(s):1468 - 1480
Cited by:  Papers (4)
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Orthogonal Matching Pursuit (OMP) is an important compressive sensing (CS) recovery and sparsity inducing algorithm, which has potential in various emerging applications ranging from wearable and mobile computing to real-time analytics processing on servers. Thus application aware OMP algorithm implementation is important. In this paper, we propose two different modifications to OMP algorithm name... View full abstract»

• ### New Algorithm for Signed Integer Comparison in ${2^{n+k},2^{n}-1,2^{n}+1,2^{npm 1}-1}$ and Its Efficient Hardware Implementation

Publication Year: 2017, Page(s):1481 - 1493
Cited by:  Papers (1)
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Sign detection and magnitude comparison are two difficult operations in Residue Number System (RNS). Existing algorithms mainly tackle either problem independently. Magnitude comparison in RNS is typically solved by parity check or transcoding the residues into weighted representation. Comparison of signed integers in residue domain is supplemented by separately designed RNS sign detector. In this... View full abstract»

• ### Efficient and Reliable Small-Signal Estimate of Quantization Noise Contribution to Phase Noise in $Delta Sigma$ Fractional- $N$ PLL

Publication Year: 2017, Page(s):1494 - 1503
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The effect of the quantization noise introduced by AΣ modulators in fractional-N phase locked loop is studied in the time domain through a variational model of the corresponding analog mixed signal circuits. The latter can be interpreted as hybrid dynamical systems involving discontinuity boundaries and switching in the vector field. Discontinuity mapping is used to define an accurate high ... View full abstract»

• ### Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs

Publication Year: 2017, Page(s):1504 - 1514
Cited by:  Papers (2)
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This paper presents a digital blind background calibration technique of imperfections in time-interleaved analog-to-digital converters (TI-ADCs). The proposed technique directly operates on the statistics of the input signal to continuously estimate and eliminate the conversion errors resulted from offset, gain, and timing mismatch. Behavioral simulations are presented for a 4-channel 10-bit TI-AD... View full abstract»

• ### Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition

Publication Year: 2017, Page(s):1515 - 1528
Cited by:  Papers (2)
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This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both estimation and correction algorithms share the common derivative filter, which makes them possible to reduce the chip area. Furthermore, these algorithms use the polyphase filtering technique and do not use adaptive digit... View full abstract»

• ### Lorentzian Based Adaptive Filters for Impulsive Noise Environments

Publication Year: 2017, Page(s):1529 - 1539
Cited by:  Papers (1)
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In this paper, three Lorentzian based robust adaptive algorithms are proposed for identifying systems in presence of impulsive noise. The first algorithm called Lorentzian adaptive filtering (LAF) is derived from a sliding window type cost function with Lorentzian norm of past errors to combat adverse effect of impulsive noise on systems. The first and second order convergence analyses of the LAF ... View full abstract»

• ### Memristor Circuits: Bifurcations without Parameters

Publication Year: 2017, Page(s):1540 - 1551
Cited by:  Papers (4)
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The present manuscript relies on the companion paper entitled “Memristor Circuits: Flux-Charge Analysis Method,” which has introduced a comprehensive analysis method to study the nonlinear dynamics of memristor circuits in the flux-charge (φ, q)-domain. The Flux-Charge Analysis Method is based on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK