# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 29

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
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• ### A Chopper Instrumentation Amplifier With Input Resistance Boosting by Means of Synchronous Dynamic Element Matching

Publication Year: 2017, Page(s):753 - 764
Cited by:  Papers (12)
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In this work, we propose a method to increase the parasitic input resistance caused by application of chopper modulation to indirect current feedback instrumentation amplifiers. The result is obtained by applying dynamic element matching to the input and feedback ports at the same frequency as chopper modulation. The proposed approach requires effective offset ripple rejection and equalization of ... View full abstract»

• ### A Quad-Band CMOS Linear Power Amplifier for EDGE Applications Using an Anti-Phase Method to Enhance its Linearity

Publication Year: 2017, Page(s):765 - 776
Cited by:  Papers (3)
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This work describes the use of an anti-phase method to enhance the linearity of a quad-band CMOS linear power amplifier for EDGE applications. The anti-phase method is applied in a CMOS process, by studying the gm3characteristic of the transistor and then operating the drive stage in the subthreshold region to cancel the nonlinearity of the power stage. The power amplifier is fabricated... View full abstract»

• ### A ± 3 ppm/°C Single-Trim Switched Capacitor Bandgap Reference for Battery Monitoring Applications

Publication Year: 2017, Page(s):777 - 786
Cited by:  Papers (4)
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A precision bandgap reference has been developed in a 0.18 μm BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 o from -40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a 2ndorder delta-sigma modulator ADC to digitize a battery cell voltage. The switched capaci... View full abstract»

• ### Nanopower, Sub-1 V, CMOS Voltage References With Digitally-Trimmable Temperature Coefficients

Publication Year: 2017, Page(s):787 - 798
Cited by:  Papers (8)
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Two variants of a MOS-only voltage reference are proposed. They are based on MOSFETs operating at a constant inversion level which cancels out nonlinearities of their temperature dependence arising from that of mobility. The theory behind the circuits is thoroughly discussed, a design method is described and experimental results are presented. The two architectures propose different trimming metho... View full abstract»

• ### A Low Energy-Noise 65nm CMOS Switched-Capacitor Resistive-Bridge Sensor Interface

Publication Year: 2017, Page(s):799 - 810
Cited by:  Papers (2)
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A low energy-noise switched-capacitor (SC) sensor interface for resistive bridge sensor is presented. The SC amplifier achieves low-power metric with two operating modes using operation-phase-dependent biasing and compensation scheme in the op-amp design. This novel op-amp works in high-bandwidth high-power mode to sample the bridge signal for 13μs twice and in low-bandwidth low-power mode for 474... View full abstract»

• ### A 2.25–2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop

Publication Year: 2017, Page(s):811 - 822
Cited by:  Papers (4)
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An area-efficient subharmonically injection-locked fractional-N frequency synthesizer is presented. The phase domain analysis confirms that a second-order subharmonically injection-locked phase-locked loop (SIPLL) can be stable even if the loop filter is composed of only a tiny capacitor. Thus, the area of the loop filter shrinks dramatically to realize an area efficient SIPLL. Besides, a fast-con... View full abstract»

• ### An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

Publication Year: 2017, Page(s):823 - 835
Cited by:  Papers (4)
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This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of... View full abstract»

• ### Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance

Publication Year: 2017, Page(s):836 - 846
Cited by:  Papers (5)
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In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the sa... View full abstract»

• ### Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

Publication Year: 2017, Page(s):847 - 857
Cited by:  Papers (23)
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In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (V<sub>dd</sub>) scaling in MTJ based NV-LIM is evaluated on... View full abstract»

• ### eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache

Publication Year: 2017, Page(s):858 - 868
Cited by:  Papers (2)
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As 2.5D/3D die stacking technology emerges, stacked dynamic random access memory (DRAM) has been proposed as a cache due to its large capacity in order to bridge the latency gap between off-chip memory and SRAM caches. The main problems in utilizing a DRAM cache are the high tag storage overhead and the high lookup latency. To address these, we propose tags-in-eDRAM (embedded DRAM) due to its high... View full abstract»

• ### Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Publication Year: 2017, Page(s):869 - 878
Cited by:  Papers (11)
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In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at... View full abstract»

• ### Half-Matrix Normal Basis Multiplier Over GF( $p^{m}$ )

Publication Year: 2017, Page(s):879 - 891
Cited by:  Papers (1)
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In this paper, we propose two new algorithms and their hardware implementations for the normal basis multiplication over GF(pm), where p ∈ {2,3}. In this case, the proposed multipliers are designed using serial and digit-serial hardware architectures. The normal basis multipliers over GF(2m) and GF(3m) are based on two proposed algorithms to compute the multiplicat... View full abstract»

• ### Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

Publication Year: 2017, Page(s):892 - 905
Cited by:  Papers (1)
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CORDIC algorithm is suitable to implement sine/cosine function, but the large number of iterations lead to great delay and overhead. Moreover, due to finite bit-width of operands and number of iterations, the relative error of floating-point sine or cosine is terrible when the input angle is close to 0 or π/2, respectively. To overcome these shortcomings, TCORDIC algorithm, which combines low late... View full abstract»

• ### Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

Publication Year: 2017, Page(s):906 - 917
Cited by:  Papers (12)
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This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type of hard-decision decoder for Low-Density Parity-Check (LDPC) code, with improved error correction performance thanks to the introduction of deliberate random perturbation in the computing units. In the PGDBF, the random perturbation opera... View full abstract»

• ### Optimization of Noise Shaping Filter for Quantizer With Error Feedback

Publication Year: 2017, Page(s):918 - 930
Cited by:  Papers (4)
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Noise shaping filters for quantizers with error feedback are designed to mitigate the effects of quantization errors. In this paper, we prove that if the transfer function from the quantization error to the signal-of-interest has minimum phase and there is no constraint on the feedback signal, then the scaled inverse of the transfer function is the optimal noise shaping filter. Next, we design a n... View full abstract»

• ### Fast and Accurate Time-Domain Simulations of Integer-N PLLs

Publication Year: 2017, Page(s):931 - 944
Cited by:  Papers (2)
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We present a methodology to simulate industrial integer-N phase-locked loops (PLLs) at a verification level, as accurate as and faster than transistor-level simulation. The accuracy is measured on the PLL factors of interest, i.e., locking time, power consumption, phase noise and jitter (period and long-term). The speedup factor tends to the division ratio N for device-noise simulations. We develo... View full abstract»

• ### Fixed-Order Piecewise-Affine Output Feedback Controller for Fuzzy-Affine-Model-Based Nonlinear Systems With Time-Varying Delay

Publication Year: 2017, Page(s):945 - 958
Cited by:  Papers (47)
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This paper studies the problem of delay-dependent fixed-order memory piecewise-affine H∞output feedback control for a class of nonlinear systems with time-varying delay via a descriptor system approach. The nonlinear plant is expressed by a continuous-time Takagi-Sugeno (T-S) fuzzy-affine model. Specifically, by utilizing a descriptor model transformation, the original closed-loop syste... View full abstract»

• ### A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis

Publication Year: 2017, Page(s):959 - 968
Cited by:  Papers (2)
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A 5-Gb/s voltage-mode (VM) transmitter using adaptive time-based de-emphasis is presented. The duty cycle of the pulse-width modulation data is adjusted by the spectrum-balancing technique. This adaptive VM transmitter does not need an auxiliary cable. It can adaptively compensate the loss of the channels with different lengths. This transmitter and a receiver are fabricated in a 40-nm CMOS proces... View full abstract»

• ### A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling

Publication Year: 2017, Page(s):969 - 980
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This paper presents a low power interference-robust radar transceiver architecture for noncontact vital sign detection and mobile healthcare applications. A duty-cycled transceiver design is proposed to significantly reduce power consumption of front-end circuits. Occupying 3-to-5 GHz band with four 500 MHz sub-channels, the radar mitigates the narrowband interference (NBI) problem with the freque... View full abstract»

• ### Design of a CML Transceiver With Self-Immunity to EMI in 0.18- $\mu$ m CMOS

Publication Year: 2017, Page(s):981 - 991
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This paper presents the design of an integrated current mode logic (CML) transceiver system that demonstrates a superior robustness to electromagnetic interference (EMI). The effect of EMI on a typical CML transceiver has been investigated and the findings are addressed in the design of the proposed CML transceiver. The typical and proposed CML transceivers are compared experimentally for EMI-robu... View full abstract»

• ### A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems

Publication Year: 2017, Page(s):992 - 1002
Cited by:  Papers (14)
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A self-body-biasing technique is proposed for differential-drive cross-coupled (DDCC) rectifier, with its profound application in far-field RF energy-harvesting systems. The conventional source-to-body, and the proposed technique known as Lower DC Feeding (LDCF), were fabricated in the 130-nm CMOS and compared at the operation frequency of 500 MHz, 953 MHz and 2 GHz along with a corresponding load... View full abstract»

• ### High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger

Publication Year: 2017, Page(s):1003 - 1012
Cited by:  Papers (1)
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In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors

Publication Year: 2017, Page(s): 1013
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK