# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2016, Page(s): C2
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• ### Out-of-Band Immunity to Interference of Single-Ended Baseband Amplifiers Through$IM_{2}$Cancellation

Publication Year: 2016, Page(s):1785 - 1793
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The effect of second-order intermodulation (IM2) distortion produced by out-of-band, high-frequency interference on baseband/IF amplifiers is analyzed using the Volterra series. It is shown that a compensation loop designed to trap nonlinear currents improves the immunity of differential stages to IM2distortion generated by local feedback. Measurements of a single-ended ampli... View full abstract»

• ### Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method

Publication Year: 2016, Page(s):1794 - 1806
Cited by:  Papers (1)
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This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped in... View full abstract»

• ### 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Publication Year: 2016, Page(s):1807 - 1815
Cited by:  Papers (16)
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A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies ... View full abstract»

• ### A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator With Digital Compensation Technique

Publication Year: 2016, Page(s):1816 - 1824
Cited by:  Papers (6)
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The design of a 12.77-MHz on-chip RC relaxation oscillator with digital compensation technique is presented. To maintain the frequency stability versus temperature and supply voltage variations, loop delay tuning by a digital feedback loop is developed in this system. In order to generate an on-chip reference for digital calibration, a replica comparator is added. The on-chip relaxation oscillator... View full abstract»

• ### Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing

Publication Year: 2016, Page(s):1825 - 1832
Cited by:  Papers (2)
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A new 96 × 96 array of 30 μm × 30 μm readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated. Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed. The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently. Thes... View full abstract»

• ### A Thin-Film, Large-Area Sensing and Compression System for Image Detection

Publication Year: 2016, Page(s):1833 - 1844
Cited by:  Papers (4)
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This paper presents a sensing and compression system for image detection, based on large-area electronics (LAE). LAE allows us to create expansive, yet highly-dense arrays of sensors, enabling integration of millions of pixels. However, the thin-film transistors (TFTs) available in LAE have low performance and high variability, requiring the sensor data to be fed to CMOS ICs for processing. This r... View full abstract»

• ### A 5 GHz Fractional-$N$ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

Publication Year: 2016, Page(s):1845 - 1853
Cited by:  Papers (3)
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An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional-N frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the timeto-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to ... View full abstract»

• ### A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Publication Year: 2016, Page(s):1854 - 1865
Cited by:  Papers (4)
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We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employ... View full abstract»

• ### A 300-$\mu\text{W}$Audio$\Delta\Sigma$Modulator With 100.5-dB DR Using Dynamic Bias Inverter

Publication Year: 2016, Page(s):1866 - 1875
Cited by:  Papers (6)
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This paper presents a micropower audio delta-sigma (ΔΣ) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation... View full abstract»

• ### A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Publication Year: 2016, Page(s):1876 - 1888
Cited by:  Papers (5)
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This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a t... View full abstract»

• ### A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs

Publication Year: 2016, Page(s):1889 - 1897
Cited by:  Papers (2)
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This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a ... View full abstract»

• ### Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs

Publication Year: 2016, Page(s):1898 - 1909
Cited by:  Papers (3)
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A practical model for characterizing comparator metastability errors in SAR ADCs is presented, and is used to analyze not only the conventional SAR but also LSB-first and asynchronous versions. This work makes three main contributions: first, it is shown that for characterizing metastability it is more reasonable to use input signals with normal or Laplace distributions. Previous work used uniform... View full abstract»

• ### A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications

Publication Year: 2016, Page(s):1910 - 1920
Cited by:  Papers (3)
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Hardware search engine (HSE) plays a major role to speed up the search operation in wireless applications. Ternary content addressable memory (TCAM) is such an engine which performs the search in a single clock cycle but the use of separate content and mask storage, various wordlines for read/mask/write, and decoupled data/search lines require substantial design area and consume relatively high po... View full abstract»

• ### Opportunistic Refreshing Algorithm for eDRAM Memories

Publication Year: 2016, Page(s):1921 - 1932
Cited by:  Papers (2)
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Embedded DRAM (eDRAM) is an alternative technology that can replace the area and power consumed by SRAM cache memories. eDRAM consumes half the area and an order of magnitude less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. This paper presents an opportunistic refreshing algorithm along with the appropriate memory architecture and skim control l... View full abstract»

• ### Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes

Publication Year: 2016, Page(s):1933 - 1943
Cited by:  Papers (6)
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Radiation effects cause several types of errors on memories including single event upsets (SEUs) or single event functional interrupts (SEFIs). Error correction codes (ECCs) are widely used to protect against those errors. For a number of reasons, there is a large interest in using double data rate type three (DDR-3) synchronous dynamic random-access (SDRAM) memories in space applications. Radiati... View full abstract»

• ### High-Throughput Low-Complexity Unified Multipliers Over $GF(2^{m})$ in Dual and Triangular Bases

Publication Year: 2016, Page(s):1944 - 1953
Cited by:  Papers (1)
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Multiplication is an essential operation in cryptographic computations. One of the important finite fields for such computations is the binary extension field. High-throughput low-complexity multiplication architectures lead to more efficient cryptosystems. In this paper, a high-throughput low-complexity unified multiplier for triangular and dual bases is presented, and is referred to as basic arc... View full abstract»

• ### An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition

Publication Year: 2016, Page(s):1954 - 1963
Cited by:  Papers (3)
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An energy-efficient fast array multiplier is proposed and designed. The multiplier operates in a left-to-right mode enabling a full overlap between reduction of partial products in carry-save form and the final addition producing the product. The design is based on the left-to-right carry-free (LRCF) multiplier. It differs from the LRCF multiplier in a much smaller on-the-fly conversion circuit of... View full abstract»

• ### Analysis and Design of Boolean Associative Memories Made of Resonant Oscillator Arrays

Publication Year: 2016, Page(s):1964 - 1973
Cited by:  Papers (2)
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This paper investigates some relevant open issues related to implementing Boolean associative memories using oscillator arrays. At the circuit level, the employment of a class of MEMS-based oscillators which is ideal for large arrays realizations is herein considered. At the system level, the crucial problems of array connectivity and spurious patterns generation are explored in detail. As a resul... View full abstract»

• ### Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks

Publication Year: 2016, Page(s):1974 - 1985
Cited by:  Papers (5)
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Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of... View full abstract»

• ### A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron

Publication Year: 2016, Page(s):1986 - 1996
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This paper presents a COordinate Rotation DIgital Computer (CORDIC) based Adaptive Exponential Integrate and Fire (AdEx) neuron for efficient large scale biological neural network implementation. The accuracy of the modified model is investigated by both calculating various errors and bifurcation analysis; both show that the proposed model follows the same signaling, dynamical behavior, and bifurc... View full abstract»

• ### Memristor Circuits: Flux—Charge Analysis Method

Publication Year: 2016, Page(s):1997 - 2009
Cited by:  Papers (34)
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Memristor-based circuits are widely exploited to realize analog and/or digital systems for a broad scope of applications (e.g., amplifiers, filters, oscillators, logic gates, and memristor as synapses). A systematic methodology is necessary to understand complex nonlinear phenomena emerging in memristor circuits. The manuscript introduces a comprehensive analysis method of memristor circuits in th... View full abstract»

• ### An Encryption Scheme Based on Synchronization of Two-Layered Complex Dynamical Networks

Publication Year: 2016, Page(s):2010 - 2021
Cited by:  Papers (13)
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A novel encryption scheme based on complex chaotic networks is proposed in this paper. Compared with a single chaotic system, a network of chaotic systems possesses complex dynamic characteristics, which can be used in encryption to enhance security. We adopt the drive-response synchronization method to synchronize two identical chaotic networks at the transmitter and receiver. Analysis on encrypt... View full abstract»

• ### One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits

Publication Year: 2016, Page(s):2022 - 2035
Cited by:  Papers (5)
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A calibration mechanism is often desired in analog/RF circuits that are designed in advance process nodes which exhibit large process variation, so as to recover yield loss and obtain the best possible trade-off between performances. In this paper, we present a calibration approach based on embedded sensors that has several appealing attributes. Specifically, it is virtually applicable to any circ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK