# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2015, Page(s): C2
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• ### Generalized Analysis of Random Common-Mode Rejection Performance of CMOS Current Feedback Instrumentation Amplifiers

Publication Year: 2015, Page(s):2137 - 2146
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The generalized CMRR analysis of the CMOS current feedback instrumentation amplifier (CFIA), in drain and source feedback configurations (termed DCFIA and SCFIA), is developed by focusing on the input stage. The random CMRR for processes (CMRRP) of the CFIAs are derived as a function of the transistor dimensions, small-signal and operating parameters, as well as the process-dependent mismatch fact... View full abstract»

• ### High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

Publication Year: 2015, Page(s):2147 - 2155
Cited by:  Papers (6)
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This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a... View full abstract»

• ### A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Publication Year: 2015, Page(s):2156 - 2166
Cited by:  Papers (1)
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This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conve... View full abstract»

• ### A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu{\rm m}$ CMOS for Medical Implant Devices

Publication Year: 2015, Page(s):2167 - 2176
Cited by:  Papers (27)
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This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the off... View full abstract»

• ### An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability

Publication Year: 2015, Page(s):2177 - 2186
Cited by:  Papers (9)
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A novel ultra-low power energy harvesting and imaging (EHI) type CMOS active pixel sensor (APS) imager with self-power capability is presented. The proposed EHI type CMOS APS pixel harvests one order of magnitude higher power than that of the other pixel technologies reported in the literature. It produces 46 μW of power under 57 klux illumination. The EHI imager presented has decoupled ima... View full abstract»

• ### A Time-Mode Translinear Principle for Nonlinear Analog Computation

Publication Year: 2015, Page(s):2187 - 2195
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This work proposes a novel translinear principle based on time domain processing of signals. The exponential relationship between voltage and time in an RC circuit is exploited to implement a logarithmic voltage-to-time converter and an exponential time-to-voltage converter. These circuits are the time domain analogs of the voltage mode translinear circuits that exploit the exponential relationshi... View full abstract»

• ### Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

Publication Year: 2015, Page(s):2196 - 2206
Cited by:  Papers (7)
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This paper analyzes the thermal and reference noises of two types of successive-approximation-register (SAR) analog-to-digital converters (ADCs): the time-interleaving (TI) and the partial-interleaving (PI) Pipelined. The thermal noise is investigated with accurate estimation by deriving closed-form expressions according to the noise equivalent models on different phases. Additionally, the design ... View full abstract»

• ### Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators

Publication Year: 2015, Page(s):2207 - 2215
Cited by:  Papers (8)
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This paper deals with modeling and simulation of a new family of two-terminal devices fabricated with vanadium dioxide material. Such devices allow realization of very compact relaxation nano-oscillators that can be connected electronically to form arrays of coupled oscillators. Challenging applications of oscillator arrays include the realization of multiphase signal generators and massively para... View full abstract»

• ### A 75 dB SNDR 10-MHz Signal Bandwidth Gm-C-Based Sigma-Delta Modulator With a Nonlinear Feedback Compensation Technique

Publication Year: 2015, Page(s):2216 - 2226
Cited by:  Papers (3)
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Wideband ( ≥10 MHz) continuous-time (CT) sigma-delta (ΣΔ) modulators generally use active-RC filters. On the other hand, Gm-C-filters avoid the need of a power-hungry driving stage due to their small loading. At the moment, the major challenge for designing Gm-C-based ΣΔ modulator is the narrow linear input range due to the nonlinear Gm amplifier, which leads to ... View full abstract»

• ### 150–850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization

Publication Year: 2015, Page(s):2227 - 2237
Cited by:  Papers (9)
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A low distortion sinusoidal waveform synthesizer architecture is proposed. The synthesizer utilizes 50% duty cycle and differential-mode circuitry to eliminate the even order harmonics, and it also implements a 5-phase 3-amplitude harmonic cancellation technique to suppress the 3rd, 5th, 7th, and 9th order harmonics. The compact system architecture consists of a 12-phase ring oscillator, a weighte... View full abstract»

• ### SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Publication Year: 2015, Page(s):2238 - 2247
Cited by:  Papers (1)
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Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced by metastability, even in the case where sufficient time is left for resolution. This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combini... View full abstract»

• ### Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS

Publication Year: 2015, Page(s):2248 - 2259
Cited by:  Papers (4)
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Many RNS-based implementations of digital signal processing algorithms have experienced the overkill of arithmetic operator sizes due to the choice of moduli set to accommodate for the occasional high precision operations. As the sizes of modulo arithmetic operators are fixed by the choice of their moduli, they are not scalable even if there is a subsequent reduction in the dynamic range. This pap... View full abstract»

• ### Efficient Implementation of Punctured Parallel Finite Field Multipliers

Publication Year: 2015, Page(s):2260 - 2267
Cited by:  Papers (1)
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Finite field multipliers are embedded in many applications. In some applications, e.g., in cryptographic primitives protected by security oriented codes, only r bits out of the m-bit product are required. In such cases, the circuit area can be significantly reduced by implementing a punctured finite field multiplier. This article deals with efficient implementation of multipliers. It is shown that... View full abstract»

• ### Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction

Publication Year: 2015, Page(s):2268 - 2279
Cited by:  Papers (12)
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This article proposes a novel adaptive architecture for blind identification and compensation of frequency response mismatches in 4-channel time-interleaved analog-to-digital-converters (TI-ADCs). Detailed frequency response mismatch modeling is first carried out elaborating in detail the interleaving mismatch spurs characteristics. Stemming from the established mirror-frequency crosstalk nature o... View full abstract»

• ### A Soft-Defined Pulse Width Modulation Approach—Part I: Principles

Publication Year: 2015, Page(s):2280 - 2289
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In this work a novel pulse width modulation (PWM) scheme is presented consisting of a mixed digital-analog implementation. The aim of this approach is to obtain maximum flexibility in setting and varying the average switching frequency, as a method to optimally deal with specifications concerning power consumption and bandwidth management. Conventional analog implementations of PWM suffer from ina... View full abstract»

• ### A Soft-Defined Pulse Width Modulation Approach—Part II: System Modeling

Publication Year: 2015, Page(s):2290 - 2300
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In this work we model from a system design perspective the realization of a novel mixed-signal approach to pulse width modulation (PWM). The working principle for the approach, along with an implementation scheme comprised of a digital zero-positioning (ZP) followed by a proper digital-to-analog converter (DAC) and comparator, has been introduced in a companion paper. We here focus on analyzing th... View full abstract»

• ### Asynchronous Consensus of Multiple Double-Integrator Agents With Arbitrary Sampling Intervals and Communication Delays

Publication Year: 2015, Page(s):2301 - 2311
Cited by:  Papers (10)
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This paper addresses asynchronous consensus problems of multiple double-integrator agents with discontinuous information transmission, where each agent receives its neighbors' state information at discrete instants determined by its own clock. A novel consensus protocol is proposed based on continuous information of each agent itself and sampled information of each agent's neighbors. By using nonn... View full abstract»

• ### Output Synchronization of Dynamical Networks with Incrementally-Dissipative Nodes and Switching Topology

Publication Year: 2015, Page(s):2312 - 2323
Cited by:  Papers (15)
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This paper studies asymptotic output synchronization for a class of dynamical networks with identical nonlinear nodes and switching topology. The node dynamics are characterized by a quadratic form of incremental-dissipativity. The output synchronization problem of the switched network is first converted into the set stability problem for the interconnected nonlinear system with a particular selec... View full abstract»

• ### A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers

Publication Year: 2015, Page(s):2324 - 2333
Cited by:  Papers (1)
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This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the... View full abstract»

• ### On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators

Publication Year: 2015, Page(s):2334 - 2341
Cited by:  Papers (10)
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The white noise to phase noise conversion of one- and two-port CMOS differential-pair harmonic oscillators with transformer-based resonators is addressed in this paper. First, the operation of double-tuned transformer resonators is reviewed and design guidelines are proposed to maximize the quality factor. A rigorous approach is then employed to approximate the transformer network with a second or... View full abstract»

• ### Predistortion of Digital RF PWM Signals Considering Conditional Memory

Publication Year: 2015, Page(s):2342 - 2350
Cited by:  Papers (3)
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The trend in transmitter systems is to move the digital domain closer towards the antenna using digital modulators and drivers to reduce circuit complexity and to save power. A common assumption made is that they are capable of generating ideal pulses and thus do not suffer from analog imperfections. But the output signals of real drivers for high frequency operation are not perfectly rectangular ... View full abstract»

• ### Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter

Publication Year: 2015, Page(s):2351 - 2360
Cited by:  Papers (2)
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This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in , and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique , to linearize the control-to-output transfer function across different ope... View full abstract»

• ### Comments on “Novel Dual-Band Matching Network for Effective Design of Concurrent Dual-Band Power Amplifiers”

Publication Year: 2015, Page(s):2361 - 2363
Cited by:  Papers (6)
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A novel dual-band matching network for concurrent dual-band power amplifiers has been proposed and discussed by Fu in January 2014. The first stage matching network effectively accomplished real-to-complex impedance transformation by utilizing a transmission line, a short-circuited stub and an open-circuited stub. However, the obtainment of the values of the electrical parameters are realized by t... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK