# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2015, Page(s): C2
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• ### Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014)

Publication Year: 2015, Page(s):1897 - 1898
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• ### Modeling of Resistance in FinFET Local Interconnect

Publication Year: 2015, Page(s):1899 - 1907
Cited by:  Papers (1)
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We present an innovative and comprehensive approach to model the resistance of local interconnect used in FinFET technologies. Our parasitic resistance formulas for FinFET source/drain regions cover both merged and unmerged fin processes. Both simple and composite local interconnect cases are studied. They have been verified with field solver simulation results, and are found to be accurate over a... View full abstract»

• ### PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog

Publication Year: 2015, Page(s):1908 - 1917
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This paper presents an event-driven simulation methodology for injection-locked oscillators. The proposed method adopts a phase-domain macromodel based on a perturbation projection vector (PPV), which expresses the oscillator's phase response using a nonlinear, time-varying differential equation. By expressing the PPV using a piecewise polynomial function, the PPV model can be simulated in an even... View full abstract»

• ### A Power Management Unit With 40 dB Switching-Noise-Suppression for a Thermal Harvesting Array

Publication Year: 2015, Page(s):1918 - 1928
Cited by:  Papers (2)
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A high efficiency, maximum power point tracking (MPPT) power management unit (PMU), with 3.6 \mmbμW quiescent power, aimed at a thermoelectric generator (TEG) array is presented. The proposed energy harvesting PMU is made up of a boost converter with a cascaded capacitor-less low drop-out (CL-LDO) voltage regulator. The segmented approach allows the PMU to match the TEG array's changing dyn... View full abstract»

• ### A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

Publication Year: 2015, Page(s):1929 - 1939
Cited by:  Papers (2)
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A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets WiGig standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a “correct-by-construction,” timing-calibration-free global bottom-plate sampling scheme. The ADC achiev... View full abstract»

• ### A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System

Publication Year: 2015, Page(s):1940 - 1949
Cited by:  Papers (8)
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A fully-integrated sensing system is proposed for wideband complex dielectric detection of materials under test (MUT). The system utilizes a ring oscillator-based phase-locked loop (PLL) for wide tuning range and precise control of the sensor's excitation frequency. Characterization of both real and imaginary MUT permittivity is achieved by measuring the frequency difference between two voltage-co... View full abstract»

• ### Matching the Power, Voltage, and Size of Biological Systems: A nW-Scale, 0.023- ${\rm mm}^{3}$ Pulsed 33-GHz Radio Transmitter Operating From a 5 kT/q-Supply Voltage

Publication Year: 2015, Page(s):1950 - 1958
Cited by:  Papers (6)
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This paper explores the extent to which a solid-state transmitter can be miniaturized, while still using RF for wireless information transfer and working with power densities and operating voltages comparable to what could be harvested from a living system. A 3.1 nJ/bit pulsed millimeter-wave transmitter, 300 μm by 300 μm by 250 μm in size, designed in 32-nm SOI CMOS, operates... View full abstract»

• ### Gain at an Arbitrary Cut in a Linear Bilateral Network, and Its Relation to Loop Gain in Feedback Amplifiers

Publication Year: 2015, Page(s):1959 - 1970
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General expressions are derived for the gain around the loop formed by cutting into an arbitrary linear bilateral network. A test signal is injected into one side of the cut, the other side is closed by an element which forces the voltages at the two sides to be equal, and the gain at the cut is the ratio of the test current to the closing current. In a dual situation the closing element forces th... View full abstract»

• ### 10-Gb/s 0.13- $\mu{\rm m}$ CMOS Inductorless Modified-RGC Transimpedance Amplifier

Publication Year: 2015, Page(s):1971 - 1980
Cited by:  Papers (6)
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This paper presents an inductorless 0.13- μm CMOS TIA structure that is a modified version of a regulated cascode (RGC) TIA. An immittance converter is incorporated to reduce power consumption while increasing transimpedance gain. Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s operation, in the presence of 250 fF capacitance at the TIA input, representative of typical CMOS photodi... View full abstract»

• ### A Generalized Model of Noise Driven Circuits with Application to Stochastic Resonance

Publication Year: 2015, Page(s):1981 - 1990
Cited by:  Papers (1)
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The paper presents a novel simulation tool which can be used for numerical analysis of nonlinear circuits and systems forced by strong noise sources and perturbed by weak periodic signals. The methodology, which is based on linear-response theory, is universal in scope and can be applied to all topologies without restraints on the dimensionality of the structure or the size of the parameter set. T... View full abstract»

• ### A High Sensitivity Analog Front-end Circuit for Semi-Passive HF RFID Tag Applied to Implantable Devices

Publication Year: 2015, Page(s):1991 - 2002
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A high sensitivity analog front-end is presented for semi-passive HF RFID tag for implantable devices. The design is compatible with the ISO/IEC 14443 Type-A. A rectifier with high power conversion efficiency is presented to provide stable rectified voltage. Novel tag system architecture with wake-up circuit is proposed to improve the sensitivity. Other Key circuits are studied and designed to mak... View full abstract»

• ### An Analog On-Line Gain Calibration Loop for RF Amplifiers

Publication Year: 2015, Page(s):2003 - 2012
Cited by:  Papers (1)
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This paper presents an analog on-line gain calibration loop for radio-frequency (RF) amplifiers. In the proposed calibration scheme, the gain of an RF amplifier is determined by programmable resistor ratios of two transimpedance amplifiers (TIAs), while the corresponding control voltage is generated through a differential difference amplifier (DDA). Being the first work to propose a continuous-tim... View full abstract»

• ### A Linearized Model for the Design of Fractional-$N$ Digital PLLs Based on Dual-Mode Ring Oscillator FDCs

Publication Year: 2015, Page(s):2013 - 2023
Cited by:  Papers (1)
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A digital fractional- N phase-locked loop (PLL) frequency synthesizer based on a second-order ΔΣ frequency-to-digital converter (FDC) without conventional analog components was recently proposed and demonstrated experimentally to have performance in line with state-of-the-art analog PLLs. However, unlike analog PLLs or prior PLLs based on second-order ΔΣ FDCs, it is hig... View full abstract»

• ### An Invasive-Attack-Resistant PUF Based On Switched-Capacitor Circuit

Publication Year: 2015, Page(s):2024 - 2034
Cited by:  Papers (5)
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An invasive-attack-resistant physical unclonable function (PUF) with strong reliability is presented. The mismatch of capacitor ratios in real fabrication is sampled by a switched-capacitor (SC) circuit and further amplified by a latch-styled sense amplifier. Transmission lines connected to the sampling capacitors are used to cover and protect the whole chip from outside invasive attacks. The prop... View full abstract»

• ### Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

Publication Year: 2015, Page(s):2035 - 2043
Cited by:  Papers (11)
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In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performanc... View full abstract»

• ### Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach

Publication Year: 2015, Page(s):2044 - 2051
Cited by:  Papers (3)
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It is well-known that the (a,b)-way Karatsuba algorithm (KA) with a ≠ b is used for efficient digit-serial multiplication with subquadratic space complexity architecture. In this paper, based on (a,b)-way KA decomposition, we have derived a novel k-way block recombination KA (BRKA) decomposition for digit-serial multiplication. The proposed k-way BRKA is formed by a power of 2 polynomial de... View full abstract»

• ### High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Publication Year: 2015, Page(s):2052 - 2061
Cited by:  Papers (2)
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This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. I... View full abstract»

• ### MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure

Publication Year: 2015, Page(s):2062 - 2068
Cited by:  Papers (7)
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We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers,... View full abstract»

• ### Data-Dependent Delays as a Barrier Against Power Attacks

Publication Year: 2015, Page(s):2069 - 2078
Cited by:  Papers (5)
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Power analysis attacks utilize the correlation between the dissipated power and the processed data. Although the instantaneous power dissipation contains information it cannot be exploited without full reverse engineering. This article explores data-dependent instantaneous (intra-cycle) power dissipation and shows that it can be used as additional source of randomness that can be utilized as a bar... View full abstract»

• ### Configurable Architectures for Multi-Mode Floating Point Adders

Publication Year: 2015, Page(s):2079 - 2090
Cited by:  Papers (1)
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This paper presents two architectures for floating point (FP) adders, which operates in multi-mode configuration with multi-precision support. First architecture (named QPdDP) works in dual-mode which can operates either for quadruple precision or two-parallel double precision. The second architecture (named QPdDPqSP) works in tri-mode which is able to compute either of a quadruple precision, two-... View full abstract»

• ### Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Publication Year: 2015, Page(s):2091 - 2102
Cited by:  Papers (1)
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Phase-change random access memory (PRAM) is considered to be one of the most promising storage class memory candidates. In this paper, several circuit techniques are introduced to satisfy the target yield and sensing time requirements of an 8-Gb PRAM. First, we propose a temperature-tracking reference current generator to compensate for the variation in data current caused by the change in the res... View full abstract»

• ### Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

Publication Year: 2015, Page(s):2103 - 2113
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The discrete wavelet transform is a fundamental block in several schemes for image compression. Its implementation relies on filters that usually require multiplications leading to a relevant hardware complexity. Distributed arithmetic is a general and effective technique to implement multiplierless filters and has been exploited in the past to implement the discrete wavelet transform as well. Thi... View full abstract»

• ### Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers

Publication Year: 2015, Page(s):2114 - 2121
Cited by:  Papers (4)
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A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20-100 MHz. The BPF is part of a cellular superheterodyne receiver and completely determines the receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK