Volume 5 Issue 1 • March 2015
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Table of Contents
Publication Year: 2015, Page(s): C1|
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IEEE Journal on Emerging and Selected Topics in Circuits and Systems publication information
Publication Year: 2015, Page(s): C2|
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Guest Editorial Computing in Emerging Technologies (Second Issue)
Publication Year: 2015, Page(s):1 - 4 -
Exploring Spin Transfer Torque Devices for Unconventional Computing
Publication Year: 2015, Page(s):5 - 16
Cited by: Papers (9)This paper reviews the potential of spin-transfer torque devices as an alternative to complementary metal-oxide-semiconductor for non-von Neumann and non-Boolean computing. Recent experiments on spin-transfer torque devices have demonstrated high-speed magnetization switching of nanoscale magnets with small current densities. Coupled with other properties, such as nonvolatility, zero leakage curre... View full abstract»
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Emitter-Coupled Spin-Transistor Logic: Cascaded Spintronic Computing Beyond 10 GHz
Publication Year: 2015, Page(s):17 - 27
Cited by: Papers (3)The cascading of logic gates is a critical challenge for the development of spintronic logic circuits. Here we propose the first logic family exploiting magnetoresistive bipolar spin-transistors to achieve a complete spintronic logic family in which logic gates can be cascaded. This logic family, emitter-coupled spin-transistor logic (ECSTL), is an extension of emitter-coupled logic (ECL) that lev... View full abstract»
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Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM
Publication Year: 2015, Page(s):28 - 39
Cited by: Papers (20) | Patents (1)The emerging spin transfer torque magnetic random access memory (STT-MRAM) promises many attractive features, such as nonvolatile, high speed and low power etc, which enable it to be a promising candidate for the next-generation logic and memory circuits. However with the continuous scaling technology process, the chip yield and reliability of STT-MRAM face severe challenges due to the increasing ... View full abstract»
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Domain Wall Magnets for Embedded Memory and Hardware Security
Publication Year: 2015, Page(s):40 - 50
Cited by: Papers (9)Domain wall memory (DWM) is one possible candidate for embedded cache application due to its multi-level cell capability, low standby power, fast access time, good endurance, and good retention. In this paper, we utilize a physics-based model of domain wall to comprehend the process variations and Joule heating that can lead to functional issues in the memory. We propose techniques to mitigate the... View full abstract»
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Phase Change Memory Write Cost Minimization by Data Encoding
Publication Year: 2015, Page(s):51 - 63
Cited by: Papers (3)Phase change memory (PCM) is a promising next generation nonvolatile memory. Despite the currently popular charge-based storage techniques, PCM leverages a much more scalable thermal-resistive mechanism that enables sub-10 nm feature sizes. To realize PCM's potential, there are a number of technical challenges that need to be addressed, including limited wear endurance and high energy consumption ... View full abstract»
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A Complementary Resistive Switch-Based Crossbar Array Adder
Publication Year: 2015, Page(s):64 - 74
Cited by: Papers (28) | Patents (1)Redox-based resistive switching devices (ReRAM) are an emerging class of nonvolatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in larg... View full abstract»
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A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies
Publication Year: 2015, Page(s):75 - 87
Cited by: Papers (2)A fast and efficient system-level design methodology is developed and validated to evaluate and optimize processors using emerging technologies at the early design stage. It includes an updated empirical cycle per instruction model, a hierarchical memory model, and several multi-level interconnection network models. Multiple device- and system-level design parameters are simultaneously optimized t... View full abstract»
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Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse
Publication Year: 2015, Page(s):88 - 97In this paper, we study the problem of mapping large applications onto hierarchical architectures based on novel nanodevices. We combine both intellectual property (IP) reuse and multi-level mapping concepts in order to cope with application complexity and reduce circuit design time. In this context, we introduce an “O-cycle” design flow that exploits the IP reuse concept for the dev... View full abstract»
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Reconfiguration-Based VLSI Design for Security
Publication Year: 2015, Page(s):98 - 108
Cited by: Papers (4)Reconfigurable computing is a critical technology for achieving nanoelectronic systems of yield and reliability. In this paper, we present that reconfigurable computing is further a critical technology for achieving hardware security in the presence of supply chain adversaries. Specifically, reconfigurable implementation of a given logic function achieves design obfuscation, while reconfiguration ... View full abstract»
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Advances in Computational Modeling of Electronic Devices Based on Graphene
Publication Year: 2015, Page(s):109 - 116
Cited by: Papers (3)Nowadays electronic devices such as p-n diodes, field-effect transistors, logic gates, mixers, ring oscillators, and memories have been designed based on single, bi and/or multi-layer graphene. However, a lot of effort must be developed to integrate mathematical models into new simulators for electronic devices based on nanomaterials such as those based on carbon nanotubes, fullerenes, and graphen... View full abstract»
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IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors
Publication Year: 2015, Page(s): 117|
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IEEE Circuits and Systems Society Information
Publication Year: 2015, Page(s): C3|
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Publication Year: 2015, Page(s): C4|
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Aims & Scope
The IEEE Journal on Emerging and Selected Topics in Circuits and Systems publishes special issues covering the entire Field of Interest of the IEEE Circuits and Systems Society and with particular focus on emerging areas.
Meet Our Editors
Editor-in-Chief
Eduard Alarcon
UPC BarcelonaTech
Barcelona, Spain
eduard.alarcon@upc.edu