# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 40

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2015, Page(s): C2
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• ### Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier

Publication Year: 2015, Page(s):617 - 624
Cited by:  Papers (11)
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Extensive power management analysis of an inductive power delivery system for medical implants with a 1X/2X reconfigurable rectifier is conducted to help achieve higher system voltage gain and higher system power transfer efficiency under different loading and coupling conditions. Input capacitance matching due to mode switching is analyzed and a matching compensation scheme is proposed. Analysis ... View full abstract»

• ### Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps

Publication Year: 2015, Page(s):625 - 634
Cited by:  Papers (2)
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Ten methods for finding through simulations the small-signal phase and gain margins of feedback circuits based on op-amps are described and analyzed in this mostly tutorial paper. The testbenches employed by these methods are presented and the corresponding analytical expressions of the return ratio are derived and compared against their “ideal” counterpart, obtained with standard circuit analysis... View full abstract»

• ### A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for$\Delta\Sigma$PLLs

Publication Year: 2015, Page(s):635 - 644
Cited by:  Papers (7)
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A low phase noise injection-locked reference clock multiplier that can suppress the delta-sigma (ΔΣ) noise of ΔΣ phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of... View full abstract»

• ### A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time$\Sigma\Delta$ADC for a Digital Closed-Loop Class-D Amplifier

Publication Year: 2015, Page(s):645 - 653
Cited by:  Papers (3)
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This paper presents a continuous-time third-order ΣΔ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed ΣΔ modulator consumes 1.7 mW f... View full abstract»

• ### PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC

Publication Year: 2015, Page(s):654 - 661
Cited by:  Papers (7)
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A digital background calibration technique to treat capacitor mismatch, residue gain error, and nonlinearity in a pipelined ADC based on the split-ADC architecture is reported. Although multiple works have been reported before on the split- calibration of pipelined ADCs, none of them is comprehensive, i.e., capacitor mismatch, residue gain error, and nonlinearity are never treated in one work at t... View full abstract»

• ### A 1.2-V 4.2-$\hbox{ppm}/^{\circ}\hbox{C}$High-Order Curvature-Compensated CMOS Bandgap Reference

Publication Year: 2015, Page(s):662 - 670
Cited by:  Papers (42)  |  Patents (1)
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This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to ... View full abstract»

• ### A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC

Publication Year: 2015, Page(s):671 - 679
Cited by:  Papers (3)
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A phase-domain analog-to-digital converter (PhADC) is a promising alternative to a pair of amplitude-domain in-phase and quadrature (IQ) ADCs for low power FSK/PSK demodulation, but the fundamental benefits and limitations of the PhADC over the IQ ADC have not been precisely quantified as yet. In this paper, analytical methods are proposed to comprehensively compare the PhADC and the IQ ADC. Phase... View full abstract»

• ### Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

Publication Year: 2015, Page(s):680 - 688
Cited by:  Papers (4)
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A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 μm CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first describ... View full abstract»

• ### A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18$\mu{\rm m}$CMOS

Publication Year: 2015, Page(s):689 - 696
Cited by:  Papers (38)
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An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-... View full abstract»

• ### An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

Publication Year: 2015, Page(s):697 - 706
Cited by:  Papers (27)
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This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumpt... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (41)
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A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time$\Sigma\Delta$ADCs

Publication Year: 2015, Page(s):717 - 724
Cited by:  Papers (6)
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Sine-shaped feedback DAC was proposed to be used in continuous-time ΣΔ ADCs for its immunity to clock jitter. However, in a sine-shaped DAC, the carrier is used as an analog signal to mix with the data, consequently, all the carrier noise appears in the sine-shaped data. The effect of carrier noise was studied before, but the analysis was based on the assumption of white noise, which is not true i... View full abstract»

• ### Optimal Tuning of Inductive Wireless Power Links: Limits of Performance

Publication Year: 2015, Page(s):725 - 732
Cited by:  Papers (10)
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This paper shows how to choose compensation capacitors for optimal performance in two-coil fixed-frequency inductive wireless power links having a series-parallel (SP) configuration. First, for the SP circuit with given coils, coupling and sinusoidal input voltage, it is shown how to calculate nonnegative valued capacitors to maximize power delivered to a given resistive load. Exact conditions for... View full abstract»

• ### A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing

Publication Year: 2015, Page(s):733 - 742
Cited by:  Papers (14)
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This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible... View full abstract»

• ### A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

Publication Year: 2015, Page(s):743 - 751
Cited by:  Papers (3)
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A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high ... View full abstract»

• ### A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

Publication Year: 2015, Page(s):752 - 760
Cited by:  Papers (3)
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In this paper, a 60 V tolerance transceiver with ESD (electrostatic discharge) protection is proposed for FlexRay-based communication systems. The FlexRay transceiver comprises three protective devices, including an over-voltage detector, high-voltage ESD devices, and high-voltage diodes. The over-voltage detector is in charge of detecting bus (BP and BM) status to distinguish whether any hazard h... View full abstract»

• ### A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

Publication Year: 2015, Page(s):761 - 770
Cited by:  Papers (3)
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This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable s... View full abstract»

• ### Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)

Publication Year: 2015, Page(s):771 - 780
Cited by:  Papers (5)
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This paper proposes highly reliable coding methods for applications in two extreme conditions. n-out-of-8 level cell (nLC) is proposed for archival applications which require significantly long data-retention time with small write/erase cycle. On the other hand, for applications with large write/erase cycle and short data-retention time (enterprise application, etc.), universal asymmetric coding (... View full abstract»

• ### Analysis and Design of a Core-Size-Scalable Low Phase Noise$LC$-VCO for Multi-Standard Cellular Transceivers

Publication Year: 2015, Page(s):781 - 790
Cited by:  Papers (2)
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A core-size-scalable LC-voltage-controlled oscillator (VCO) for multi-standard cellular transceivers was fabricated in a 65-nm CMOS process. Theoretical analysis showed that when core current is small a VCO with a larger core-size can achieve lower phase noise. However, when core current is large, a VCO with a smaller core-size can lower phase noise. Based on the analysis, the effective core-size ... View full abstract»

• ### Superregenerative Reception of Narrowband FSK Modulations

Publication Year: 2015, Page(s):791 - 798
Cited by:  Papers (3)
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In this paper we investigate the possibilities of narrowband FSK detection using a superregenerative (SR) receiver. Previous SR FM demodulation techniques rely on detecting the amplitude variations caused by the different frequencies involved in FSK modulation. However, this requires relatively high frequency deviations because the frequency response of SR receivers is not very selective. In this ... View full abstract»

• ### An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip

Publication Year: 2015, Page(s):799 - 806
Cited by:  Papers (15)
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This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications. Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier. Novel dual gain-boosting techniques improve the gain, ba... View full abstract»

• ### Selective State Retention Power Gating Based on Formal Verification

Publication Year: 2015, Page(s):807 - 815
Cited by:  Papers (1)
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This work is aimed to reduce the area and power consumption in low-power VLSI design. A new selective approach for State Retention Power Gating (SRPG) based on Module Checking formal verification techniques is presented, and so-called Selective SRPG (SSRPG). The proposed approach is applied in order to minimize the number of retention flip flops required for state retention during sleep mode. The ... View full abstract»

• ### An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model

Publication Year: 2015, Page(s):816 - 824
Cited by:  Papers (3)
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The heat equation and the electrothermal equation are widely used in chip design, and generally supposed to be equivalent. We prove this equivalence in mathematical manner, but show that it is only valid when the boundary condition is convective. Recent technologies have a much increased leakage power, which is highly temperature-dependent. The modified thermal equations which model this dependenc... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK