# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2014, Page(s): C2
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• ### Thoughts on Possible Future Charge-Based Technologies for Nano-Electronics

Publication Year: 2014, Page(s):3057 - 3065
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Scaling of silicon-based devices cannot continue indefinitely. As a result, various groups have been working on replacements for conventional CMOS. The most close to production-worthy of these include the carbon-based options of graphene (planar single layer sheets of graphite), and carbon nanotube technologies, and also compound semiconductor-based tunnel fets (TFETs). These new devices can, in p... View full abstract»

• ### Current Feedback Linearization Applied to Oscillator Based ADCs

Publication Year: 2014, Page(s):3066 - 3074
Cited by:  Papers (2)
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A regulation scheme to linearize the tuning curve of CMOS ring oscillators is proposed in this paper. The scheme uses the current consumption of the CMOS ring elements, which is proportional to the output frequency to the first order. The design of the feedback loop is presented on system level in conjunction with performance enhancements made on the implementation level. A weakly non-linear ring ... View full abstract»

• ### Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Publication Year: 2014, Page(s):3075 - 3084
Cited by:  Papers (4)
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Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and... View full abstract»

• ### A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors

Publication Year: 2014, Page(s):3085 - 3093
Cited by:  Papers (16)
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A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additi... View full abstract»

• ### Compact Analog Temporal Edge Detector Circuit With Programmable Adaptive Threshold for Neuromorphic Vision Sensors

Publication Year: 2014, Page(s):3094 - 3104
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This paper presents a low-power compact analog circuit for processing time varying signals. The proposed circuit implements temporal differentiation, amplification and rectification, i.e., separation of outputs into on and off pathways. It is based on a hysteretic differentiator circuit, commonly used in neuromorphic vision sensors to implement temporal edge detection. This paper presents a thorou... View full abstract»

• ### A 0.13-$\mu{\rm m}$ CMOS Low-Power Capacitor-Less LDO Regulator Using Bulk-Modulation Technique

Publication Year: 2014, Page(s):3105 - 3114
Cited by:  Papers (11)
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In this paper, a bulk-modulation technique is introduced for improving the performance of low-drop-out (LDO) voltage regulators. Compared to conventional LDO voltage regulators, the proposed circuit achieves improved accuracy, stability, and output load current capability. The technique is particularly suited for low-power applications such as biomedical implants and portable devices. A proof-of-c... View full abstract»

• ### Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b,2)-Way Karatsuba Decomposition

Publication Year: 2014, Page(s):3115 - 3124
Cited by:  Papers (11)
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Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two variations of polynomial basis representation. SPB/GPB have potential for efficient bit-level and digit-level implementations of multiplication over binary extension fields. This paper presents a (b,2)-way KA decomposition for digit-serial multiplication with low-space complexity. Based on the proposed parallel (b,2)-way... View full abstract»

• ### Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier

Publication Year: 2014, Page(s):3125 - 3134
Cited by:  Papers (6)
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Karatsuba algorithm (KA) is popularly used for high-precision multiplication of long binary polynomials. The only well-known subquadratic multipliers using KA scheme are, however, based on conventional two-operand polynomial multiplication. In this paper, we propose a novel approach based on 2-way and 3-way KA decompositions for computing three-operand polynomial multiplications. Using these novel... View full abstract»

• ### A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems

Publication Year: 2014, Page(s):3135 - 3144
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We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on... View full abstract»

• ### A Versatile Data Cache for Trace Buffer Support

Publication Year: 2014, Page(s):3145 - 3154
Cited by:  Papers (3)
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Since the cache system has been a predominant part in modern SoC's and its capacity is sometimes larger than necessary for specific applications, it is desirable to enhance the role of the cache system to beyond its original purpose (performance improvement). In this paper we propose a versatile data cache, called DT (data/trace) cache, by making it to function simultaneously as a regular data cac... View full abstract»

• ### Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Publication Year: 2014, Page(s):3155 - 3164
Cited by:  Papers (14)
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The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near- VT) or even to the subthreshold (sub- VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy di... View full abstract»

• ### Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement

Publication Year: 2014, Page(s):3165 - 3174
Cited by:  Papers (3)
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A PRAM write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 k Ω, and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times... View full abstract»

• ### A Low Energy and High Performance ${\rm DM}^{2}$ Adder

Publication Year: 2014, Page(s):3175 - 3183
Cited by:  Papers (2)
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A novel Dual Mode Square (DM2) adder is proposed. The DM2 adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide... View full abstract»

• ### Reduction of Aliasing Effects of RF PWM Modulated Signals by Cross Point Estimation

Publication Year: 2014, Page(s):3184 - 3192
Cited by:  Papers (4)
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The trend in transmitter systems is to move the digital domain closer toward the antenna using digital modulators and drivers to reduce circuit complexity and to save power. One promising approach is the use of RF pulse width modulation (RF PWM). Unfortunately purely digital discrete time RF PWM suffers from aliasing problems which limit the achievable resolution. For a 40 MHz bandwidth signal at ... View full abstract»

• ### Reconfigurable Quantization of Oversampled Signals Under Discrete-Time Filtering

Publication Year: 2014, Page(s):3193 - 3205
Cited by:  Papers (2)
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In modern wireless applications such as carrier aggregation, oversampled ADCs are required to be reconfigurable, to accommodate varying spectral signal energy distributions and bandwidths of interest. While progress has been made using several circuit and system level techniques, a fundamental approach that considers the signal's spectral properties is lacking. In this paper, we re-evaluate the ov... View full abstract»

• ### Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique

Publication Year: 2014, Page(s):3206 - 3215
Cited by:  Papers (11)
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Multiplierless FIR filter optimization has been extensively studied in the past decades to minimize the number of adders. A more accurate measurement of the implementation complexity is the number of full adders counted at bit-level. However, the high computational complexity of the optimization at bit-level hinders the technique from practical applications. In this paper, the sparse filter techni... View full abstract»

• ### Recovering Structures of Complex Dynamical Networks Based on Generalized Outer Synchronization

Publication Year: 2014, Page(s):3216 - 3224
Cited by:  Papers (11)
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The topological structures of complex networks play a crucial role in determining their evolutionary mechanisms and functional behaviors, and may have significant consequences for many real-world applications. Many researchers focused on the geometric features, collective behaviors and control of complex networks provided with precisely known structures. However, the exact topology of a network is... View full abstract»

• ### Optimal Polygonal $L_{1}$ Linearization and Fast Interpolation of Nonlinear Systems

Publication Year: 2014, Page(s):3225 - 3234
Cited by:  Papers (3)
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The analysis of complex nonlinear systems is often carried out using simpler piecewise linear representations of them. A principled and practical technique is proposed to linearize and evaluate arbitrary continuous nonlinear functions using polygonal (continuous piecewise linear) models under the L1 norm. A thorough error analysis is developed to guide an optimal design of two kinds of polygonal a... View full abstract»

• ### Restricted Partial Stability and Synchronization

Publication Year: 2014, Page(s):3235 - 3244
Cited by:  Papers (2)
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In this paper we combine partial stability and set invariance methods, which is a necessary development for applications such as synchronization. We use set invariance methods to ensure that the `auxiliary' variables remain on a restricted domain, and then use this framework to develop new results for both local and global partial stability theory. We apply the methodology to identical synchroniza... View full abstract»

• ### ${\cal H}_{\infty}$ Pinning Synchronization of Directed Networks With Aperiodic Sampled-Data Communications

Publication Year: 2014, Page(s):3245 - 3255
Cited by:  Papers (51)
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This paper addresses the global H∞ pinning synchronization problem for a class of directed networks with aperiodic sampled-data communications. Important yet challenging issues of how many and which nodes should be pinned for realizing global synchronization in a fixed directed network without external disturbances are first discussed. By using a combined tool from the input-dela... View full abstract»

• ### RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors

Publication Year: 2014, Page(s):3256 - 3265
Cited by:  Papers (4)
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This paper describes the first purely digital approach to reduce the receive band noise in digitally-intensive RF transmitters. The proposed solution applies bandpass delta-sigma modulation and dynamic element matching (DEM) to the receive band (RX-band) instead of the transmit band. This enables selective attenuation of the noise originating from amplitude quantization and static mismatches of th... View full abstract»

• ### A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

Publication Year: 2014, Page(s):3266 - 3277
Cited by:  Papers (5)
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A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1-1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45-5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reco... View full abstract»

• ### A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

Publication Year: 2014, Page(s):3278 - 3287
Cited by:  Papers (4)
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This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternativel... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK