# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 36

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2014, Page(s): C2
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• ### A Signal- and Transient-Current Boosting Amplifier for Large Capacitive Load Applications

Publication Year: 2014, Page(s):2777 - 2785
Cited by:  Papers (17)
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A signal- and transient-current boosting (STCB) circuit is proposed and applied to a single-stage amplifier driving large capacitive loads. The proposed STCB circuit provides gain-bandwidth product (GBW) extension, slew-rate (SR) improvement and gain enhancement to the amplifier, with only slight alterations to the frequency response and transient response of the single-stage amplifier driving lar... View full abstract»

• ### Self-Calibrated Knee Voltage Detector With 99.65% High Accuracy for AC Charger System in 0.5$\mu{\rm m}$500 V UHV Process

Publication Year: 2014, Page(s):2786 - 2795
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The self-calibrated knee voltage detector (SC-KVD) for electrical isolation primary side charger applications is proposed. The removal of the feedback network which is used in conventional designs and occupies at least 30 mm2can save PCB area up to around 11%. Besides, the SC-KVD can dynamically adjust the detection point to improve the accuracy to 99.65% compared to the prior arts. The... View full abstract»

• ### Noise-Shaped Residue-Discharging Delta-Sigma ADCs With Time-Modulated Pulse Feedback

Publication Year: 2014, Page(s):2796 - 2804
Cited by:  Papers (4)
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This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the c... View full abstract»

• ### A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration

Publication Year: 2014, Page(s):2805 - 2815
Cited by:  Papers (6)
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A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of +0.76/ -0.68 LSB and a DNL of +0.72/ -0.68 LSB. Its ENOB is 5.25 bits at Nyquist input fr... View full abstract»

• ### Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

Publication Year: 2014, Page(s):2816 - 2824
Cited by:  Papers (7)
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The Single Electron Transistor holds the potential to be a suitable readout device for future solid-state quantum computers. The low temperature measurement results of a 0.5 μm Silicon-On-Sapphire CMOS circuit designed to interface with a Single Electron Transistor are presented. Careful design of the experimental set-up is critical for conducting the circuit test and performance measurements at c... View full abstract»

• ### FPN Attenuation by Reset-Drain Actuation in the Linear-Logarithmic Active Pixel Sensor

Publication Year: 2014, Page(s):2825 - 2833
Cited by:  Papers (7)
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The three FET CMOS active pixel sensors (APS) operating in the linear-logarithmic mode is one of the most efficient wide-dynamic-range imagers. However, the quality of the image generated at the focal-plane array is often compromised by fixed-pattern noise (FPN) between pixels. The classical correlated double sampling (CDS) technique is used to reduce FPN in imagers operating in the linear mode. B... View full abstract»

• ### Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism

Publication Year: 2014, Page(s):2834 - 2841
Cited by:  Papers (4)
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Content addressable memory (CAM) is widely used in many applications, especially for those applications needing fast memory access. However, due to the parallel comparison feature and the frequent precharge/discharge of match-lines, the power consumption of CAM is considerable. In this paper, a fast and automatic charge balancing CAM architecture is proposed to control the voltage swing of match-l... View full abstract»

• ### A Fused Floating-Point Three-Term Adder

Publication Year: 2014, Page(s):2842 - 2850
Cited by:  Papers (7)
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This paper presents improved architectures for a fused floating-point three-term adder. The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. In order to further improve the performance of the three-term adder,... View full abstract»

• ### Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Publication Year: 2014, Page(s):2851 - 2861
Cited by:  Papers (25)
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Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as n-type or p-type by controlling the polarity gate voltage. This paper extends this approach by using th... View full abstract»

• ### A 1.35-V 16-Mb Twin-Bit-Cell Virtual-Ground-Architecture Embedded Flash Memory With a Sensing Current Protection Technique

Publication Year: 2014, Page(s):2862 - 2868
Cited by:  Papers (1)
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In this paper, a 1.35 V 16 Mb twin-bit-cell virtual ground architecture embedded Flash memory is presented. To reduce the sensing margin loss caused by the side-leakage current in the virtual ground architecture memory array, a sensing current protection technique has been proposed. A reference voltage generating circuit for dynamic sensing window tracking is designed to maximize the sensing windo... View full abstract»

• ### Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

Publication Year: 2014, Page(s):2869 - 2877
Cited by:  Papers (9)
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This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory ban... View full abstract»

• ### Universal Hardware for Systems With Acceptable Representations as Low Order Polynomials

Publication Year: 2014, Page(s):2878 - 2887
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This paper presents a novel hardware architecture for adaptive systems whose exact specification is unknown. The architecture is suitable for linear and nonlinear systems whose inputs are real or complex signals (variables), and that have an acceptable representation as low order polynomials in these variables. The implementation is based on using an a priori selected subset of Walsh spectral coef... View full abstract»

• ### A Floating Memristor Emulator Based Relaxation Oscillator

Publication Year: 2014, Page(s):2888 - 2896
Cited by:  Papers (33)
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In this paper, a flux-controlled memristor emulator with floating terminals by making use of four current conveyors is newly proposed. By replacing the three resistors in the positive and negative feedback loops of a typical relaxation oscillator respectively, three cases of memristor emulator based oscillating circuits are theoretically constructed and mathematically analyzed. To further probe th... View full abstract»

• ### Time-Delayed Chaotic Circuit Design Using All-Pass Filter

Publication Year: 2014, Page(s):2897 - 2903
Cited by:  Papers (3)
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The all-pass filter method is proposed to approximately realize time-delayed chaotic electronic circuits. The amplitude-frequency characteristic and group time delay of the all-pass filter are analyzed and compared with the known low-pass filter. The number of filters in cascade is evaluated. Using the all-pass filter method, the infinite-dimensional time-delayed nonlinear system is reduced to fin... View full abstract»

• ### Locking Range Derivations for Injection-Locked Class-E Oscillator Applying Phase Reduction Theory

Publication Year: 2014, Page(s):2904 - 2911
Cited by:  Papers (10)
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This paper presents a numerical locking-range prediction for the injection-locked class-E oscillator using the phase reduction theory (PRT). By applying this method to the injection-locked class-E oscillator designs, which is in the field of electrical engineering, the locking ranges of the oscillator on any injection-signal waveform can be efficiently obtained. The locking ranges obtained from th... View full abstract»

• ### Phase Noise of Pulse Injection-Locked Oscillators

Publication Year: 2014, Page(s):2912 - 2919
Cited by:  Papers (9)
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Sub-harmonic pulse injection-locked oscillators are becoming attractive candidates for the design of clock multipliers and as building blocks of phase-locked loops. Unfortunately, due to the large amplitude of the injected signals, these circuits cannot be analyzed with conventional methods and very-time-consuming simulations are needed to determine their phase noise performance. Phase-noise simul... View full abstract»

• ### On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Publication Year: 2014, Page(s):2920 - 2930
Cited by:  Papers (4)
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Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32 nm technology. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Since varying the supply voltage also causes the BTI degradation to vary over lifetime, this presents a new challenge for margin reducti... View full abstract»

• ### Robust Synchronization via Homogeneous Parameter-Dependent Polynomial Contraction Matrix

Publication Year: 2014, Page(s):2931 - 2940
Cited by:  Papers (5)
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Robust synchronization problem is a key issue in chaotic circuits and nonlinear systems. This paper is concerned with robust synchronization problem of polynomial nonlinear system affected by time-varying uncertainties on topology, i.e., structured uncertain parameters constrained in a bounded-rate polytope. Via partial contraction analysis, novel conditions, both for robust exponential synchroniz... View full abstract»

• ### Highest Degree Likelihood Search Algorithm Using a State Transition Matrix for Complex Networks

Publication Year: 2014, Page(s):2941 - 2950
Cited by:  Papers (6)
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Since complex network theory was first put forward, the search issue for networks has drawn increasing attention from multidisciplinary researchers, and has played an important role in network study. Many practical applications require search algorithms such as searching for the shortest relationship link in social networks, seeking web sites on the Internet, and finding specified files in data se... View full abstract»

• ### Generalized Semi-Analytical Design Methodology of Class-E Outphasing Power Amplifier

Publication Year: 2014, Page(s):2951 - 2960
Cited by:  Papers (6)
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This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed ... View full abstract»

• ### High-Throughput Cognitive-Amplification Detector for LDPC Decoders

Publication Year: 2014, Page(s):2961 - 2969
Cited by:  Papers (2)
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With the advent of technology over the recent years, the low-density parity-check (LDPC) codes, which were once seen as an impractical concept, are now poised to be the next big thing in the communication standards of today for their near-capacity performances. Nonetheless, the physical implementation of LDPC decoders is more often than not encumbered by the arithmetic of its decoding algorithm. E... View full abstract»

• ### Analysis and Design of CMOS Received Signal Strength Indicator

Publication Year: 2014, Page(s):2970 - 2977
Cited by:  Papers (5)
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This paper presents a CMOS received signal strength indicator (RSSI) based on the successive detection architecture. Theoretical analyses of the RSSI value, error, and dynamic range are developed. The RSSI value relates to the single-stage voltage gain and the saturated output voltage level of each limiting ampifier cell. The RSSI error depends only on the single-stage voltage gain and the RSSI dy... View full abstract»

• ### Design Method of Class-F Power Amplifier With Output Power of$-$20 dBm and Efficient Dual Supply Voltage Transmitter

Publication Year: 2014, Page(s):2978 - 2986
Cited by:  Papers (4)
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The efficiency of power amplifiers (PAs) with a small output power (POUT) for short-range wireless sensor networks is limited by the loss in matching networks. To achieve high efficiency, a new design method which calculates the complicated design parameters in a class-F PA with a merged filter and matching networks is proposed. The design method provides a new quantitative conclusion that reducin... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK