# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2014, Page(s): C2
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• ### Single Transistor Active Filters: What is Possible and What is Not

Publication Year: 2014, Page(s):2517 - 2524
Cited by:  Papers (5)
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This paper systematically investigates the design of single transistor second-order active filters out-lining all possible architectures and possible impedance settings using an exhaustive MAPLE search code for all stable cases with the minimum number of passive elements (two resistors and two energy storage elements). The search is performed on six general voltage-input voltage-output transfer fu... View full abstract»

• ### Quantization Noise Reduction Techniques for Digital Pulsed RF Signal Generation Based on Quadrature Noise Shaped Encoding

Publication Year: 2014, Page(s):2525 - 2536
Cited by:  Papers (3)
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The digital generation of pulsed radio frequency (RF) signals based on noise shaped encoding in complex baseband is a popular concept in digital RF transmitters. However, as the pulsed complex-baseband signals are up-converted to an RF frequency, a conjugate image overlaps with the signal band, which complicates the center frequency tuning for the transmitters in question. In this paper novel ways... View full abstract»

• ### A Harmonic Class-C CMOS VCO-Based on Low Frequency Feedback Loop: Theoretical Analysis and Experimental Results

Publication Year: 2014, Page(s):2537 - 2549
Cited by:  Papers (7)
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A novel harmonic Class-C CMOS VCO architecture with improved phase noise performance and power efficiency is presented in this paper. The VCO is based on the widely adopted topology consisting in a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The Class-C operation mode is obtained through a low frequency fee... View full abstract»

• ### A Low-Power Multifunctional CMOS Sensor Node for an Electronic Facade

Publication Year: 2014, Page(s):2550 - 2559
Cited by:  Papers (4)
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In this paper, a low-power, multifunctional CMOS smart sensor node is designed for an electronic facade, which provides an alternative solution to the concept of energy-efficient responsive buildings. Various sensing capabilities, including light intensity sensing, temperature sensing, motion tracking, and compressive image acquisition, are implemented on the sensor node. An 80 × 80 image p... View full abstract»

• ### Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter

Publication Year: 2014, Page(s):2560 - 2568
Cited by:  Papers (14)
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It has been studied that, an N-path switched-capacitor (SC) branch driven by an N-phase non-overlapped local oscillator (LO), is equivalent to a tunable parallel-RLC tank suitable for radio-frequency (RF) filtering. This paper proposes a gain-boosted N-path SC bandpass filter (GB-BPF) with a number of sought features. It is based on a transconductance amplifier (Gm) with an N-path SC branch as its... View full abstract»

• ### Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations

Publication Year: 2014, Page(s):2569 - 2577
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The CP-PLL is a common component in modern communication circuits. It is used among others in frequency synthesis, synchronization and clock and data recovery. Since the CP-PLL constitutes a mixed-signal architecture and a nonlinear behavior, it is difficult to use general theories to characterize the dynamic behavior of this feedback system. Therefore, linear continuous-time and linear discrete-t... View full abstract»

• ### 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Publication Year: 2014, Page(s):2578 - 2585
Cited by:  Papers (18)
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This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity b... View full abstract»

• ### Tunable CMOS Delay Gate With Improved Matching Properties

Publication Year: 2014, Page(s):2586 - 2595
Cited by:  Papers (5)
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This paper presents the analysis and design of a tunable CMOS delay gate with improved matching properties as compared with the commonly used “current starved inverter” (CSI). The main difference between these structures lies in the location of the current limiting transistor on the inverter's output rather than on the side of the power rail. This improves the dynamic performance of ... View full abstract»

• ### Modeling of Retention Time for High-Speed Embedded Dynamic Random Access Memories

Publication Year: 2014, Page(s):2596 - 2604
Cited by:  Papers (3)
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Embedded dynamic random access memory (eDRAM) is becoming a popular choice for large cache applications due to its density, speed, and power benefits. One of the crucial challenges in eDRAM design is meeting the retention time specification. Due to implementation in logic process, usually eDRAM suffers from poor retention time compared to commodity DRAM. The retention time of eDRAM designed in sca... View full abstract»

• ### A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element

Publication Year: 2014, Page(s):2605 - 2613
Cited by:  Papers (26)
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The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high re... View full abstract»

• ### A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems

Publication Year: 2014, Page(s):2614 - 2623
Cited by:  Papers (3)
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The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but s... View full abstract»

• ### Performance Analysis of the CS-DCSK/BPSK Communication System

Publication Year: 2014, Page(s):2624 - 2633
Cited by:  Papers (17)
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As a spread spectrum communication system, code-shifted differential chaos shift keying (CS-DCSK) is required to provide reasonable bit error performance in a coexisting scenario where the conventional communication system is an interferer. Meantime, the bit error performance of the conventional communication system should not deteriorate dramatically in the presence of a CS-DCSK signal, which is ... View full abstract»

• ### A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Publication Year: 2014, Page(s):2634 - 2643
Cited by:  Papers (9)
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Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic ... View full abstract»

• ### A Krein Space Approach to $H_{\infty}$ Filtering of Discrete-Time Nonlinear Systems

Publication Year: 2014, Page(s):2644 - 2652
Cited by:  Papers (4)
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In this paper, a Krein space approach to finite horizon H∞ filtering is proposed for a class of affine nonlinear discrete-time systems. It is shown that the problem of H∞ nonlinear filtering can be converted into a minimum of an indefinite quadratic form. Hence, a relationship between H∞ nonlinear filter in Hilbert space and nonlinear estimatio... View full abstract»

• ### Multimode Oscillations in Coupled Oscillators With High-Order Nonlinear Characteristics

Publication Year: 2014, Page(s):2653 - 2662
Cited by:  Papers (2)
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We propose two van der Pol oscillators with high-order nonlinearities coupled with an inductor and investigate various types of multimode oscillations. We confirm that these oscillations are stably excited by numerical calculations, theoretical analyses and circuit experiments. In particular, we aim to show relations between the multimode oscillations and the number of order nonlinear characterist... View full abstract»

• ### Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip

Publication Year: 2014, Page(s):2663 - 2676
Cited by:  Papers (9)
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The thermal wall for many-core systems on-chip calls for advanced management techniques to maximize performance, while capping temperatures. Distributed and compact thermal models are a cornerstone for such techniques. System identification methodologies allow to extract models directly from the target device thermal response. Unfortunately, standard Auto-Regressive eXogenous models and Least Squa... View full abstract»

• ### Synchronization of Nonlinear Circuits in Dynamic Electrical Networks With General Topologies

Publication Year: 2014, Page(s):2677 - 2690
Cited by:  Papers (19)
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Sufficient conditions are derived for global asymptotic synchronization in a system of identical nonlinear electrical circuits coupled through linear time-invariant (LTI) electrical networks. In particular, the conditions we derive apply to settings where: i) the nonlinear circuits are composed of a parallel combination of passive LTI circuit elements and a nonlinear voltage-dependent current sour... View full abstract»

• ### A SAW-Less Receiver Front-End Employing Body-Effect Control IIP2 Calibration

Publication Year: 2014, Page(s):2691 - 2698
Cited by:  Papers (2)
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An IM2 product cancellation technique that employs a body-effect control of transistors is presented by developing a design for low-cost and high-linearity receiver front-end in LTE/WCDMA applications. To accomplish a high IIP2 for strong out-of-band blockers, the body terminal voltage of the mixer switches is properly adjusted to provide intentional asymmetry and suppress the IM2 at the mixer out... View full abstract»

• ### High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

Publication Year: 2014, Page(s):2699 - 2710
Cited by:  Papers (10)
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This work focuses on the VLSI design aspect of high- speed maximum a posteriori (MAP) probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the logarithmic-Bahl-Cocke-Jelinek-Raviv (LBCJR) algorithm used in MAP decoders, we have presented an ungrouped backward recursion technique for the computation of backward state metrics. Unlike the conventional decoder archi... View full abstract»

• ### Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

Publication Year: 2014, Page(s):2711 - 2720
Cited by:  Papers (1)
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This paper proposes a novel decoding algorithm to enhance the throughput of turbo decoding in LTE-Advanced systems and its hardware realization. The proposed method completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not deg... View full abstract»

• ### A 5.4 $\mu{\rm W}$ Soft-Decision BCH Decoder for Wireless Body Area Networks

Publication Year: 2014, Page(s):2721 - 2729
Cited by:  Papers (4)
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This paper presents an IEEE 802.15.6 compliant soft-decision BCH decoder for energy-constrained wireless body area networks. The proposed soft-decision decoder (SDD) provides a 1 dB coding gain compared to the hard-decision decoder (HDD). The improvement in BER performance can translate into power savings at the transmitter. The energy dissipation and area of the soft-decision BCH decoder is minim... View full abstract»

• ### Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems

Publication Year: 2014, Page(s):2730 - 2737
Cited by:  Papers (3)
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Wireless communication technology continues to advance at a rapid pace, and researchers have made tremendous progress in extending single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems such as IEEE 802.11n, WiMAX, and LTE. However, a MIMO system requires a detector circuit to separate received data. To reduce the number of comparators required, the method of mo... View full abstract»

• ### A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

Publication Year: 2014, Page(s):2738 - 2746
Cited by:  Papers (11)
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This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK