# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 37

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2014, Page(s): C2
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• ### Guest EditorialSpecial Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)

Publication Year: 2014, Page(s):2217 - 2218
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• ### A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions

Publication Year: 2014, Page(s):2219 - 2228
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The nonlinearity of an element can be altered while retaining the original operating point and first-order terms by appropriately combining multiple instances of the nonlinear element. Each instance of the combination is biased at the same operating point as the original element, but is driven by a scaled version of incremental signal present across the latter. Maintaining the sum of scaling facto... View full abstract»

• ### A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation

Publication Year: 2014, Page(s):2229 - 2235
Cited by:  Papers (2)
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Full chip mixed-signal validation requires simulating the entire design through a large number of test vectors, which makes fast, event-based Verilog models of analog circuits essential. We describe an extensible approach to creating these models that maps continuous signals into piecewise linear waveforms by creating analog events which contain a value and slope. By breaking analog circuits into ... View full abstract»

• ### Mismatch Characterization of Small Metal Fringe Capacitors

Publication Year: 2014, Page(s):2236 - 2242
Cited by:  Papers (7)
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Even though small metal fringe capacitors are important for the realization of a variety of circuits, including low-energy analog-to-digital converters and digitally controlled oscillators, the present literature is lacking experimental data on their mismatch characteristics. This paper describes a test structure and measurement results pertaining to the characterization of single-layer, lateral-f... View full abstract»

• ### Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

Publication Year: 2014, Page(s):2243 - 2252
Cited by:  Papers (10)
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The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuits increasingly susceptible to large-scale process variations. On-chip self-healing has been proposed as a promising remedy to address the variability issue. The key idea of on-chip self-healing is to adaptively adjust a set of on-chip tuning knobs (e.g., bias voltage) in order to satisfy all ... View full abstract»

• ### A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS

Publication Year: 2014, Page(s):2253 - 2262
Cited by:  Papers (19)
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CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is detrimental to the design of RF and mm-wave systems. Higher sensitivity to process variations and inaccuracies in modeling of active and passive devices pose another challenge to the design of these systems at deep submicron technology nodes. This paper describes the desig... View full abstract»

• ### A Reconfigurable $DeltaSigma$ ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling

Publication Year: 2014, Page(s):2263 - 2271
Cited by:  Papers (8)
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A reconfigurable 65-nm continuous-time low-pass delta-sigma modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10 MHz to 100 MHz, and a dynamic range of 75.4 dB to 62.8 dB, respectively. Flash ADC calibration and reference shuffling with zipper rotation are used to improve the linearity of the flash, while also increasing the highest sampling rate and ba... View full abstract»

• ### A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC

Publication Year: 2014, Page(s):2272 - 2280
Cited by:  Papers (4)  |  Patents (1)
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This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the ≥10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower bas... View full abstract»

• ### A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator

Publication Year: 2014, Page(s):2281 - 2289
Cited by:  Papers (6)
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This paper presents a second-order ΔΣ time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performanc... View full abstract»

• ### A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

Publication Year: 2014, Page(s):2290 - 2298
Cited by:  Papers (3)
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Dynamic adaptation using Razor-based detection and correction of timing errors has demonstrated substantial improvements in performance and energy-efficiency in microprocessors. In this work, we apply Razor to hardware accelerators that find increasing application in System-on-Chip designs with high-performance requirements that must be delivered under stringent power budgets. We describe the impl... View full abstract»

• ### Energy Barrier Model of SRAM for Improved Energy and Error Rates

Publication Year: 2014, Page(s):2299 - 2308
Cited by:  Papers (1)
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We propose an energy barrier model of Static Random Access Memory (SRAM). The model provides useful insights about memory error rates for write, read, and retention. We introduce the concept of intrinsic energy margin induced write failure. The proposed model is employed for evaluating various write and read assist mechanisms and their potential in modulating the memory failures. Our analysis reve... View full abstract»

• ### Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip

Publication Year: 2014, Page(s):2309 - 2317
Cited by:  Papers (4)
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A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme... View full abstract»

• ### Gate Stack Resistance and Limits to CMOS Logic Performance

Publication Year: 2014, Page(s):2318 - 2325
Cited by:  Papers (2)
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The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON), high K metal gate first stacks (GF), and high K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measuremen... View full abstract»

• ### An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space

Publication Year: 2014, Page(s):2326 - 2336
Cited by:  Papers (14)
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This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space ... View full abstract»

• ### A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

Publication Year: 2014, Page(s):2337 - 2347
Cited by:  Papers (6)
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A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 μm CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed co... View full abstract»

• ### Energy and Latency Optimization in NEM Relay-Based Digital Circuits

Publication Year: 2014, Page(s):2348 - 2359
Cited by:  Papers (8)
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Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. This paper presents a detailed analysis of the operating characteristics of fabricated curved cantilever NEM relays using a comprehensive physical model. The mode of energy distribution within the electrical and mechanical operational d... View full abstract»

• ### Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD

Publication Year: 2014, Page(s):2360 - 2369
Cited by:  Papers (6)
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Storage class memories (SCMs) are fast and energy-efficient solid-state memories with high endurance. However, the bit cost of SCM is higher than that of NAND flash memory due to its relative production immaturity. As a cost-effective alternative to replace the conventional NAND flash-only solid-state drive (SSD), the hybrid SCM/MLC NAND SSD is a promising next generation storage solution. It is a... View full abstract»

• ### Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm

Publication Year: 2014, Page(s):2370 - 2379
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This paper first presents a decomposition scheme to reduce the computation time and make the first-order moment-based cyclic convolution well suited for hardware implementation. By decomposing the fixed convolution kernel into similar subparts and using their preprocessing results as control signals, each subpart of cyclic convolution can be calculated with a basic computing substructure. Due to t... View full abstract»

• ### Designing Hyperchaotic Systems With Any Desired Number of Positive Lyapunov Exponents via A Simple Model

Publication Year: 2014, Page(s):2380 - 2389
Cited by:  Papers (35)
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This paper introduces a new and unified approach for designing desirable dissipative hyperchaotic systems. Based on the anti-control principle of continuous-time systems, a nominal system of n (n ≥ 5) independent first-order linear differential equations are coupled through all state variables, making the controlled system be in a closed-loop cascade-coupling form, where each equation conta... View full abstract»

• ### Memristor Crossbar Architecture for Synchronous Neural Networks

Publication Year: 2014, Page(s):2390 - 2401
Cited by:  Papers (16)
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This paper focuses on suitable architecture and neural network training using crossbar connections of memristive elements. We developed a novel memristor training scheme that preserves high density of synaptic connections in the crossbar organization. We designed supporting circuits and performed time domain analog simulation of the architecture, to demonstrate that it properly adjusts memristor v... View full abstract»

• ### Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices

Publication Year: 2014, Page(s):2402 - 2410
Cited by:  Papers (28)
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Highly accurate and predictive models of resistive switching devices are needed to enable future memory and logic design. Widely used is the memristive modeling approach considering resistive switches as dynamical systems. Here we introduce three evaluation criteria for memristor models, checking for plausibility of the I-V characteristics, the presence of a sufficiently nonlinearity of the switch... View full abstract»

• ### Direct Synthesis of General Chebyshev Bandpass Filters in the Bandpass Domain

Publication Year: 2014, Page(s):2411 - 2421
Cited by:  Papers (7)
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Conventional synthesis technique for general Chebyshev bandpass filters usually derives filtering polynomials from general Chebyshev filtering function. Then, lowpass prototypes or coupling matrices in the lowpass domain are derived and are transformed into the bandpass domain for practical application. Unfortunately, it has some disadvantages such as incapability to synthesize filters with asymme... View full abstract»

• ### Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers

Publication Year: 2014, Page(s):2422 - 2432
Cited by:  Papers (5)
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This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More spec... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK