# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 35

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2014, Page(s): C2
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• ### 88-$mu$ A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors

Publication Year: 2014, Page(s):1905 - 1916
Cited by:  Papers (8)
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The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensi... View full abstract»

• ### Electromagnetic Interference Resisting Operational Amplifier

Publication Year: 2014, Page(s):1917 - 1927
Cited by:  Papers (6)
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This work proposes a robust electromagnetic interference (EMI) analog operational amplifier (OpAmp) based on a source-buffered differential pair. The proposed EMI performance has been verified via a test integrated circuit (IC) fabricated in NCSU 0.5 μm CMOS technology. Experimental results are presented when an EMI disturbance signal of 800 mV amplitude is injected at the input terminals a... View full abstract»

• ### A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches

Publication Year: 2014, Page(s):1928 - 1941
Cited by:  Papers (4)
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A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-pl... View full abstract»

• ### Analysis and Design of a High Voltage Integrated Class-B Amplifier for Ultra-Sound Transducers

Publication Year: 2014, Page(s):1942 - 1951
Cited by:  Papers (6)
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Pulsers are usually adopted in ultra-sound applications due to their high efficiency. On the other hand, linear amplifiers would enable apodization profiles with high resolution, beams with low harmonic content and instantaneous changes in transmit energy between pulses. Their use is rather limited when relying on a discrete technology approach, due to high manufacturing costs and space occupation... View full abstract»

• ### A 128-Stage Analog Accumulator for CMOS TDI Image Sensor

Publication Year: 2014, Page(s):1952 - 1961
Cited by:  Papers (16)
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The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fa... View full abstract»

• ### SCDVP: A Simplicial CNN Digital Visual Processor

Publication Year: 2014, Page(s):1962 - 1969
Cited by:  Papers (5)
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In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatia... View full abstract»

• ### Variation Aware Sleep Vector Selection in Dual ${\rm V}_{{{\rm t}}}$ Dynamic OR Circuits for Low Leakage Register File Design

Publication Year: 2014, Page(s):1970 - 1983
Cited by:  Papers (4)
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Dual threshold voltage (Vt) technique is applied widely in dynamic OR circuits to achieve low leakage in register files (RF) design, but its effectiveness is significantly influenced by the selected sleep vector during the standby mode. As technology scales into deep nanometer era, the sleep vector selection in dual Vt dynamic OR (DV-OR) circuits becomes challenging due to the impact of PVT (proce... View full abstract»

• ### Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

Publication Year: 2014, Page(s):1984 - 1993
Cited by:  Papers (7)
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A multiplier-less architecture based on algebraic integer representation for computing the Daubechies 6-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using brute-force numerical optimization of the algebraic integer representation.... View full abstract»

• ### Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology

Publication Year: 2014, Page(s):1994 - 2001
Cited by:  Papers (11)
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In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-12T) using 12 transistors is proposed to provide enough immunity against single event upset in TSMC 65 nm CMOS technology. The obtained results show that the proposed cell can not only tolerate upset at its any sensitive node regardless of upset polarity and strength, but also recover from multiple-node upset ... View full abstract»

• ### Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)

Publication Year: 2014, Page(s):2002 - 2012
Cited by:  Papers (6)
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This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, th... View full abstract»

• ### Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

Publication Year: 2014, Page(s):2013 - 2021
Cited by:  Papers (3)
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Switching speed, active power consumption, standby leakage current, and silicon area are major concerns in buffer design. A new Skewed-IO cell with two split inputs and two split outputs is proposed for low-leakage and high-speed buffer design in this paper. The triple-threshold-voltage buffers with the new Skewed-IO cells offer up to 68.3% and 13.2% reduction in standby leakage currents and propa... View full abstract»

• ### Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations

Publication Year: 2014, Page(s):2022 - 2033
Cited by:  Papers (8)
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An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN)... View full abstract»

• ### Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip

Publication Year: 2014, Page(s):2034 - 2047
Cited by:  Papers (6)
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Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the ro... View full abstract»

Publication Year: 2014, Page(s):2048 - 2056
Cited by:  Papers (13)
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A new class of affine-projection-like (APL) adaptive-filtering algorithms is proposed. The new algorithms are obtained by eliminating the constraint of forcing the a posteriori error vector to zero in the affine-projection algorithm proposed by Ozeki and Umeda. In this way, direct or indirect inversion of the input signal matrix is not required and, consequently, the amount of computation required... View full abstract»

• ### Stochastic Modeling of Nonlinear Circuits via SPICE-Compatible Spectral Equivalents

Publication Year: 2014, Page(s):2057 - 2065
Cited by:  Papers (27)
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This paper presents a systematic approach for the statistical simulation of nonlinear networks with uncertain circuit elements. The proposed technique is based on spectral expansions of the elements' constitutive equations (I-V characteristics) into polynomial chaos series and applies to arbitrary circuit components, both linear and nonlinear. By application of a stochastic Galerkin method, the st... View full abstract»

• ### Gas Discharge Lamps Are Volatile Memristors

Publication Year: 2014, Page(s):2066 - 2073
Cited by:  Papers (14)
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Discharge lamps can be classified as high-pressure and low-pressure lamps, which operate under different scientific principles. They have exhibited the well-known fingerprints of memristors. This paper describes the mathematical models of both of high- and low-pressure discharge lamps based on their respective physical nature and behaviors, and then explains how these models can be unified into a ... View full abstract»

• ### A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-$mu{rm m}$ CMOS

Publication Year: 2014, Page(s):2074 - 2087
Cited by:  Papers (6)
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This paper presents a ultra-wideband (UWB) impulse radio timed-array radar utilizing time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the receiver determines the time of arrival (TOA), and a four-element timed antenna array enables beamforming. The different time shifts among the channels at the receiver determine the object's direction of arri... View full abstract»

• ### Wideband Digital Predistortion Using Spectral Extrapolation of Band-Limited Feedback Signal

Publication Year: 2014, Page(s):2088 - 2097
Cited by:  Papers (27)
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With the ever increasing demands for higher data rate, wider bandwidth is required for improving the throughput. This trend, however, imposes design challenges for the digital predistortion (DPD) in many aspects. In order to sample the broadband power amplifier (PA) output signal, it requires the use of high-speed analog-to-digital converters (ADCs), which tend to be the most expensive components ... View full abstract»

• ### An Analysis of Phase Noise in Transformer-Based Dual-Tank Oscillators

Publication Year: 2014, Page(s):2098 - 2109
Cited by:  Papers (9)
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This paper introduces a new phase noise analysis for one-port and two-port dual mode transformer-based (T-based) oscillators. In this paper we differentiate through linear time variant analysis between the noise response of L-based oscillators and dual-tank dual-mode T-based oscillators. Through derivations, we show that the open loop quality factor definition, commonly used in LC oscillators, is ... View full abstract»

• ### A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems

Publication Year: 2014, Page(s):2110 - 2118
Cited by:  Papers (3)
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Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most l... View full abstract»

• ### Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators

Publication Year: 2014, Page(s):2119 - 2128
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The analysis of a low-power, temperature- and supply voltage-independent oscillator based on a pulsed LC tank is presented. The frequency is determined by a bondwire inductor and a MiM capacitor to obtain a high-Q LC tank. Due to a novel way of driving the LC tank, the power consumption is reduced. Since the driving technique only interacts with the LC tank during a very short period, the frequenc... View full abstract»

• ### An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”

Publication Year: 2014, Page(s):2129 - 2138
Cited by:  Papers (11)
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This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in captur... View full abstract»

• ### A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

Publication Year: 2014, Page(s):2139 - 2149
Cited by:  Papers (3)
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This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm2. Current-mode-logic (CML) circuits with shunt peaking loads using cust... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK