# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2013, Page(s):C1 - C4
| PDF (149 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2013, Page(s): C2
| PDF (134 KB)
• ### An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth

Publication Year: 2013, Page(s):2813 - 2822
Cited by:  Papers (4)
| | PDF (2101 KB) | HTML

A spread-spectrum clock generator (SSCG) is realized by an under-damping all-digital phase-locked loop (PLL). In this SSCG, the spread-spectrum clocking is achieved by switching the divider without a delta-sigma modulator. By using a digital self-calibration technique, the frequency of this SSCG has a triangular modulation profile and relaxes the process variations. This SSCG is fabricated in a 0.... View full abstract»

• ### Modeling Oscillator Injection Locking Using the Phase Domain Response

Publication Year: 2013, Page(s):2823 - 2833
Cited by:  Papers (15)
| | PDF (1861 KB) | HTML

This paper presents a simulation-based model for the behavior of injection-locked oscillators (ILOs) that can be applied to any oscillator topology under any strength of injected signal. By using the phase domain response (PDR) of an oscillator, the proposed model is shown to accurately predict the behavior of ILOs with asymmetric lock ranges or those using injection into multiple locations. It ca... View full abstract»

• ### A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

Publication Year: 2013, Page(s):2834 - 2844
Cited by:  Papers (17)
| | PDF (1643 KB) | HTML

This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the ... View full abstract»

• ### A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits

Publication Year: 2013, Page(s):2845 - 2856
Cited by:  Papers (46)
| | PDF (3594 KB) | HTML

A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog cir... View full abstract»

• ### A Deep Investigation of the Synchronization Mechanisms in LC-CMOS Frequency Dividers

Publication Year: 2013, Page(s):2857 - 2866
Cited by:  Papers (15)
| | PDF (2339 KB) | HTML

The behavior of LC-CMOS frequency dividers is investigated in depth obtaining a new and clearer insight into the synchronization phenomenon. We show that it occurs according to two mechanisms, which are referred to as “synchronization by mixing” and “synchronization by harmonics.” This latter, still not known, may be the dominant mechanism in some practical circuits, and justifies the presence of ... View full abstract»

• ### An N-Path Enhanced-Q Tunable Filter With Reduced Harmonic Fold Back Effects

Publication Year: 2013, Page(s):2867 - 2877
Cited by:  Papers (11)  |  Patents (2)
| | PDF (2840 KB) | HTML

A high-Q, tunable, bandpass filtered amplifier structure is proposed which is based on a novel Q enhancement technique in N-path filters. Using Fourier series analysis, frequency response of an N-path filter as well as the aliasing effects which are present in it are derived. Frequency translation of unwanted contents at higher frequencies to the center frequency of the bandpass filter is called h... View full abstract»

• ### Nonlinear Phase-Domain Macromodeling of Injection-Locked Frequency Dividers

Publication Year: 2013, Page(s):2878 - 2887
Cited by:  Papers (3)
| | PDF (2571 KB) | HTML

This paper describes an original nonlinear phase-domain macromodel of Injection-Locked Frequency Dividers which are driven by a nonlinear input device that produces heavy harmonic distortion. These non-harmonic frequency dividers can provide wide lock ranges, however their analysis is complicated by the strong nonlinear behavior for which the hypothesis of weak injection does not apply. The propos... View full abstract»

• ### A Study of Subtractive Digital Dither in Single-Stage and Multi-Stage Quantizers

Publication Year: 2013, Page(s):2888 - 2901
Cited by:  Papers (6)
| | PDF (2299 KB) | HTML

The effect of subtractive digital dither on single-stage and multi-stage quantizers is examined. In the single stage case, it is proved that the conditional density of the quantization error becomes asymptotically independent of the input and uniformly distributed as the number of digital dither levels increases. For a fixed number of levels, the conditional expectation of a class of piecewise con... View full abstract»

• ### A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC

Publication Year: 2013, Page(s):2902 - 2910
Cited by:  Papers (6)
| | PDF (1817 KB) | HTML

A 10-bit 200 MS/s pipeline ADC using the capacitor-sharing concept is presented. A charge-neutralization technique is proposed between the 1st and 2nd MDACs to mitigate the memory effect. To further enhance power efficiency, a reference precharge technique is proposed between the 2nd and 3rd MDACs. The prototype ADC in 90-nm low-power CMOS process exhibits an INL of + 1.59/-1.91 LSB and a DNL of +... View full abstract»

• ### Frequency Synthesizer With Dual Loop Frequency and Gain Calibration

Publication Year: 2013, Page(s):2911 - 2919
Cited by:  Papers (6)  |  Patents (1)
| | PDF (2138 KB) | HTML

A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 μm CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ( KVCO of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump... View full abstract»

• ### A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization

Publication Year: 2013, Page(s):2920 - 2931
Cited by:  Papers (11)  |  Patents (1)
| | PDF (3548 KB) | HTML

This paper presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-... View full abstract»

• ### Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs

Publication Year: 2013, Page(s):2932 - 2939
Cited by:  Papers (14)
| | PDF (1822 KB) | HTML

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-... View full abstract»

Publication Year: 2013, Page(s):2940 - 2952
Cited by:  Papers (8)
| | PDF (3242 KB) | HTML

Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication. Two multi-modulus multipliers that reuse the hardware resources amongst the modulo 2n-1, modulo 2nand modulo 2n+1 multipliers by virtue of their a... View full abstract»

• ### Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation

Publication Year: 2013, Page(s):2953 - 2961
Cited by:  Papers (7)
| | PDF (2178 KB) | HTML

Through measurements from 82 test chips, each with a state retention block of 8192 flip-flops, implemented using 65-nm design library, we demonstrate that state integrity of a flip-flop is sensitive to process, voltage, and temperature (PVT) variation. It has been found at 25°C that First Failure Voltage (FFV) of flip-flops varies from die to die, ranging from 245 mV to 315 mV, with 79% of total d... View full abstract»

• ### A Novel Modulo$2^{n}-2^{k}-1$Adder for Residue Number System

Publication Year: 2013, Page(s):2962 - 2972
Cited by:  Papers (12)
| | PDF (2753 KB) | HTML

Modular adder is one of the key components for the application of residue number system (RNS). Moduli set with the form of 2n-2k-1 (1 ≤ k ≤ n-2) can offer excellent balance among the RNS channels for multi-channels RNS processing. In this paper, a novel algorithm and its VLSI implementation structure are proposed for modulo 2n-2k-1 adder. In the proposed... View full abstract»

• ### Signal Detection in Generalized Gaussian Noise by Nonlinear Wavelet Denoising

Publication Year: 2013, Page(s):2973 - 2986
Cited by:  Papers (6)
| | PDF (4344 KB) | HTML

In this paper, a nonlinear suboptimal detector whose performance in heavy-tailed noise is significantly better than that of the matched filter is proposed. The detector consists of a nonlinear wavelet denoising filter to enhance the signal-to-noise ratio, followed by a replica correlator. Performance of the detector is investigated through an asymptotic theoretical analysis as well as Monte Carlo ... View full abstract»

• ### Single-Stage and Cascade Design of High Order Multiplierless Linear Phase FIR Filters Using Genetic Algorithm

Publication Year: 2013, Page(s):2987 - 2997
Cited by:  Papers (21)
| | PDF (1643 KB) | HTML

In this work, a novel genetic algorithm (GA) is proposed for the design of multiplierless linear phase finite impulse response (FIR) filters. The filters under consideration are of high order and wide coefficient wordlength. Both the single-stage and cascade form are considered. In a practical filter design problem, when the filter specification is stringent, requiring high filter order and wide c... View full abstract»

• ### On the Passivity of Polynomial Chaos-Based Augmented Models for Stochastic Circuits

Publication Year: 2013, Page(s):2998 - 3007
Cited by:  Papers (9)
| | PDF (2414 KB) | HTML

This paper addresses for the first time the issue of passivity of the circuit models produced by means of the generalized polynomial chaos technique in combination with the stochastic Galerkin method. This approach has been used in literature to obtain statistical information through the simulation of an augmented but deterministic instance of a stochastic circuit, possibly including distributed t... View full abstract»

• ### Three Fingerprints of Memristor

Publication Year: 2013, Page(s):3008 - 3021
Cited by:  Papers (169)
| | PDF (4736 KB) | HTML

This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency in... View full abstract»

• ### A Volterra-Based Procedure for Multi-Port and Multi-Zone GaN FET Amplifier CAD Simulation

Publication Year: 2013, Page(s):3022 - 3032
Cited by:  Papers (2)
| | PDF (2790 KB) | HTML

This paper reports a systematic method for the computer-aided-design (CAD) simulation of GaN FET power amplifiers (PAs). The core of the proposal is a Volterra-based behavioral model (BM) with multi-spectral and multi-node capabilities, which black-box structure is formally derived from a circuit-level representation of the PA and accounts for both short and long-term memory effects. Starting with... View full abstract»

• ### Adaptive Pinning Control of Networks of Circuits and Systems in Lur'e Form

Publication Year: 2013, Page(s):3033 - 3042
Cited by:  Papers (42)
| | PDF (2108 KB) | HTML

This paper is concerned with the derivation of a distributed adaptive control strategy for synchronization and consensus of networks of nonlinear systems in the Lur'e form. In particular, time-varying feedback coupling and control gains are considered, whose derivatives are functions of local error over each edge in the network. The strategy is shown to be successful in controlling the network to ... View full abstract»

• ### A UHF-RFID Transceiver With a Blocker-Canceller Feedback and +30 dBm Output Power

Publication Year: 2013, Page(s):3043 - 3054
Cited by:  Papers (8)
| | PDF (2622 KB) | HTML

A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as +10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A +30 dBm class-AB power amplifier (... View full abstract»

• ### On the Modeling and Linearization of a Concurrent Dual-Band Transmitter Exhibiting Nonlinear Distortion and Hardware Impairments

Publication Year: 2013, Page(s):3055 - 3068
Cited by:  Papers (26)  |  Patents (1)
| | PDF (2897 KB) | HTML

This paper proposes a novel, complexity-reduced, dual-input, two-box model for the modeling and digital predistortion of a dual-band power amplifier (PA) in the presence of in-phase/quadrature (I/Q) modulator imperfections. The model is composed of two cascaded nonlinear blocks. The first block is implemented as a mildly nonlinear dual-input truncated Volterra filter, which includes second-order c... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK