# IEEE Transactions on Circuits and Systems I: Regular Papers

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Displaying Results 1 - 25 of 29

Publication Year: 2013, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2013, Page(s): C2
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• ### Design of $2 times {rm V}_{rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 times {rm V}_{rm DD}$ Thin-Oxide Devices

Publication Year: 2013, Page(s):2549 - 2560
Cited by:  Papers (8)
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A new 2×VDD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1 xVDD devices can successfully transmit and receive 2×VDD signal. Utilizi... View full abstract»

• ### Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State (‘X’) Elimination

Publication Year: 2013, Page(s):2561 - 2571
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Global convergence failures (GCFs), accounting for many of the start-up failures in analog/mixed-signal (AMS) systems, occur when a nonlinear circuit starts from a poorly initialized state. That is, a circuit may or may not converge to the correct mode of operation depending on how it is started upon power-on. This paper proposes a practical procedure to eliminate the uncertainty of initial states... View full abstract»

• ### A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors

Publication Year: 2013, Page(s):2572 - 2583
Cited by:  Papers (20)  |  Patents (1)
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Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC... View full abstract»

• ### A 100-Channel 1-mW Implantable Neural Recording IC

Publication Year: 2013, Page(s):2584 - 2596
Cited by:  Papers (44)  |  Patents (1)
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This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channe... View full abstract»

• ### Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs

Publication Year: 2013, Page(s):2597 - 2605
Cited by:  Papers (4)
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This paper analyzes the spurs due to delay line (DL) buffer mismatch errors and phase quantization errors in a digital-to-time conversion (DTC) direct frequency synthesizer. Applying the time/frequency axis scaling property of the Discrete Fourier Transform (DFT) to a close approximation of the general case of both buffer error and quantization error spurs, it is shown that the spur spectra for al... View full abstract»

• ### A 4th Order 3.6 GS/s RF /spl Sigma//spl Delta/ ADC With a FoM of 1 pJ/bit

Publication Year: 2013, Page(s):2606 - 2617
Cited by:  Papers (17)
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A 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the ... View full abstract»

• ### A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates

Publication Year: 2013, Page(s):2618 - 2630
Cited by:  Papers (3)
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This paper presents a logical effort delay and power model for high-speed current-mode logic (CML) circuits. Current density centric and voltage swing dependent logical effort parameters are defined in terms of the characteristic current density for peak transistor cutoff frequency, which remains relatively constant across different technology nodes. Based on this model, constant and non-constant ... View full abstract»

• ### Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

Publication Year: 2013, Page(s):2631 - 2643
Cited by:  Papers (5)
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Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products are partitioned into the (n-z)-bit least sig... View full abstract»

• ### Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

Publication Year: 2013, Page(s):2644 - 2656
Cited by:  Papers (28)  |  Patents (1)
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This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of... View full abstract»

• ### Stochastic Synchronization of Complex Networks With Mixed Impulses

Publication Year: 2013, Page(s):2657 - 2667
Cited by:  Papers (34)
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In this paper, stochastic synchronization is studied for complex networks with delayed coupling and mixed impulses. Mixed impulses are composed of desynchronizing and synchronizing impulses. The delayed coupling term involves transmission delay and self-feedback delay. By using the average impulsive interval approach and the comparison principle, several conditions are derived to guarantee that ex... View full abstract»

• ### A Unified Approach to Practical Consensus with Quantized Data and Time Delay

Publication Year: 2013, Page(s):2668 - 2678
Cited by:  Papers (76)
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In this paper, we study the consensus problem of multi-agent networks subject to communication constrains. Undirected and weighted network is considered here. Two types of communication constrains are discussed in this paper: i) each agent can only exchange quantized data with its neighbors and ii) each agent can only obtain the delayed information from its neighbors. The main contribution of this... View full abstract»

• ### Delay-Induced Consensus and Quasi-Consensus in Multi-Agent Dynamical Systems

Publication Year: 2013, Page(s):2679 - 2687
Cited by:  Papers (42)
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This paper studies consensus and quasi-consensus in multi-agent dynamical systems. A linear consensus protocol in the second-order dynamics is designed where both the current and delayed position information is utilized. Time delay, in a common perspective, can induce periodic oscillations or even chaos in dynamical systems. However, it is found in this paper that consensus and quasi-consensus in ... View full abstract»

• ### Composite Behavior of Multiple Memristor Circuits

Publication Year: 2013, Page(s):2688 - 2700
Cited by:  Papers (30)
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Composite characteristics of the parallel and serial connections of memristors are investigated. The memristor is one of the fundamental electrical elements, which has recently been successfully built. However, its electrical characteristics are not yet fully understood. When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult... View full abstract»

• ### Generalized Analysis of Symmetric and Asymmetric Memristive Two-Gate Relaxation Oscillators

Publication Year: 2013, Page(s):2701 - 2708
Cited by:  Papers (25)
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Memristive oscillators are a novel topic in nonlinear circuit theory, where the behavior of the reactive elements is emulated by the memristor. This paper presents symmetric and asymmetric memristive two-gate relaxation oscillators. First, the analysis of the two series memristors is introduced to study the effect of changing their polarities, as well as the mobility factor to be used in the two-g... View full abstract»

• ### Global Exponential Adaptive Synchronization of Complex Dynamical Networks With Neutral-Type Neural Network Nodes and Stochastic Disturbances

Publication Year: 2013, Page(s):2709 - 2718
Cited by:  Papers (34)
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This paper is on the design problem of global exponential adaptive synchronization for a class of stochastic complex dynamical networks. In the considered networks, the dynamics of each node are approximated by a neutral-type neural network. The stochastic disturbances are described in terms of Brownian motions. Different from the prior references, the coefficient matrix of the adaptive controller... View full abstract»

• ### High Precision LC Ladder Synthesis Part II: Immittance Synthesis With Transmission Zeros at DC and Infinity

Publication Year: 2013, Page(s):2719 - 2729
Cited by:  Papers (11)
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In this paper, a novel, high precision bandpass LC ladder synthesis algorithm is presented. The new algorithm directly works on the rational form of a positive real driving point input immittance F(p)=a(p)/b(p) which describes a bandpass LC ladder network in resistive termination. In the new method, firstly, poles at p=0 are removed from F(p), then remaining poles at infinity are extracted. After ... View full abstract»

• ### A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band

Publication Year: 2013, Page(s):2730 - 2739
Cited by:  Papers (8)
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In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified mult... View full abstract»

• ### Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change

Publication Year: 2013, Page(s):2740 - 2751
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In a wireless receiver, a down-converted RF signal undergoes a transient phase shift, when the gain state is changed to adjust for varying conditions in transmission and propagation. A method is developed, in which such phase shifts are detected asynchronously, and their undesirable effects on the bit error rate are corrected. The method was developed for and used in, the system-level characteriza... View full abstract»

• ### Real-Time Digital PWM With Zero Baseband Distortion and Low Switching Frequency

Publication Year: 2013, Page(s):2752 - 2762
Cited by:  Papers (6)
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A discrete-time pulse width modulator (PWM) with zero baseband distortion for arbitrary band-limited modulating signals is developed in this paper. It is based on adjusting the duty-cycles of the PWM such that the samples of an ideal low-pass filtered version of the PWM signal coincide with the discrete-time samples of the modulating signal. Elaborating on previous approaches in the literature, it... View full abstract»

• ### A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems

Publication Year: 2013, Page(s):2763 - 2773
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This paper proposes a low-overhead space-time block code (STBC) interference canceller for high-mobility STBC-orthogonal frequency division multiplexing (STBC-OFDM) systems. The proposed STBC interference canceller combined with the two-stage channel estimator can be applied to wireless metropolitan area network (WMAN), like IEEE 802.16e system. At the vehicle speeds of 240 km/hr for 16 quadrature... View full abstract»

• ### Efficient Switching Power Amplifiers Using the Distributed Switch Architecture

Publication Year: 2013, Page(s):2774 - 2787
Cited by:  Papers (1)
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Wireless transmitters employing switching power amplifiers are popular both in RF and mm-wave designs. The efficiency of switching power amplifiers is dictated mainly by the maximum achievable switch size which in turn is governed by the switch transition frequency (tradeoff between switch on-resistance and capacitance). This paper presents a new architecture, the distributed switching power ampli... View full abstract»

• ### Power Loss and Switching Noise Reduction Techniques for Single-Inductor Multiple-Output Regulator

Publication Year: 2013, Page(s):2788 - 2798
Cited by:  Papers (9)
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A new gate drive circuit to reduce the power loss and switching noise of single-inductor-multiple-output regulators is presented. Efficiency degradation and switching noise induced by the cross-talk of the voltages and currents within the power stage and buffer are analyzed. A shoot-through-current (STC) controlled buffer with four-transistor (4T) inverters is presented, and the 4T inverter enable... View full abstract»

• ### A Gain/Efficiency-Improved Serial-Parallel Switched-Capacitor Step-Up DC–DC Converter

Publication Year: 2013, Page(s):2799 - 2809
Cited by:  Papers (12)
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A new scheme of a gain/efficiency-improved serial- parallel switched-capacitor converter (SPSCC) is proposed by combining an adaptive-conversion-ratio (ACR) and pulse-width- modulation (PWM) control for step-up DC-DC conversion. For improving gain, the power part consists of one mc-stage cell and one nc-stage cell in cascade to obtain the step-up gain of (mc+1)�... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK