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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 8 • Date Aug. 2013

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Displaying Results 1 - 25 of 31
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2013 , Page(s): C2
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  • Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012)

    Publication Year: 2013 , Page(s): 1977 - 1978
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  • A 7-bit, 1.4 GS/s ADC With Offset Drift Suppression Techniques for One-Time Calibration

    Publication Year: 2013 , Page(s): 1979 - 1990
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    This paper describes a digitally calibrated 7-bit, 1.4 GS/s flash analog-to-digital converter (ADC) implemented in 45-nm CMOS. The proposed offset drift suppression techniques for dynamic comparator and preamplifier make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary, even under VDD or temperature variations. The robustness is theoretically and experimentally verified. A calibration algorithm for doubling the ADC accuracy is also presented. The ADC occupies a small area of 0.085 mm2 and dissipates 33.24 mW at 1.4 GS/s from a 1.15 V supply. View full abstract»

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  • A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation

    Publication Year: 2013 , Page(s): 1991 - 2000
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    A highly linear oscillator is presented for wideband polar modulation. It has both a varactor voltage tuning input for frequency locking and temperature compensation of phase locked loop (PLL) as well as an inductive current tuning input for linear phase modulation of PLL. Implemented in 65 nm CMOS technology, it achieved a frequency tuning gain variation of less than ±2% over more than 32 MHz frequency range meeting the WCDMA polar modulation requirement. At 3.8 GHz and 3 MHz offset, its phase noise is -136.5 dBc/Hz with current consumption of 18 mA from 2.1 V supply. View full abstract»

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  • Analysis and Design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz Divide-by-4 Injection-Locked Frequency Divider With Harmonic Boosting

    Publication Year: 2013 , Page(s): 2001 - 2008
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1998 KB) |  | HTML iconHTML  

    A locking-range enhancement technique is proposed for divide-by-4 injection-locked frequency dividers (ILFDs) at millimeter-wave frequencies. The working principle of the conventional divide-by-4 ILFDs is analyzed and verified with simulations to show that the limited locking range is mainly attributed to low efficiency of harmonic mixing. Based on the observation, an enhancement technique is developed by employing a properly-designed 4th-order LC tank to boost the 3rd-order harmonic tone at the output to increase the injection efficiency and thus the locking range. Implemented in a 65-nm CMOS process, a divide-by-4 ILFD prototype with the proposed harmonic boosting technique measures a locking range of 21.9% from 58.53 GHz to 72.92 GHz while consuming 2.2 mW from a 0.6 V supply, which corresponds to FoM of 6.54. View full abstract»

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  • A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

    Publication Year: 2013 , Page(s): 2009 - 2017
    Cited by:  Papers (3)
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    A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. View full abstract»

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  • Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays

    Publication Year: 2013 , Page(s): 2018 - 2029
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2448 KB) |  | HTML iconHTML  

    This paper reports the first analog integrated spatio-spectral beamforming front-end. The proposed front-end allows for accurate beam steering of signals with large fractional bandwidths, thus minimizing beam squinting, and simultaneous and independent steering of multi-carrier signals. Different spatio-spectral beamforming strategies are discussed and compared. As a proof of concept, an 8 GHz 2-channel, 4-frequency phased-array beamformer is designed and implemented in 65 nm CMOS. The IF signal on each channel is frequency split using an all passive 4-point analog FFT. The orthogonal frequency outputs are then beam-steered using an all passive I-Q vector-combiner. The RF circuit draws 22.8 mA from a 1.2 V supply while the analog baseband consumes 135 μW at 120 MS/s (9 pJ/conv.). View full abstract»

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  • A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode

    Publication Year: 2013 , Page(s): 2030 - 2038
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    A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing standby power at times when only a fraction of the entire memory is utilized. Measurement results from a 64 kb eDRAM test chip in 65 nm CMOS demonstrate the effectiveness of the proposed circuit techniques. View full abstract»

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  • A Low-Cost Audio Computer for Information Dissemination Among Illiterate People Groups

    Publication Year: 2013 , Page(s): 2039 - 2050
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    We present Literacy in Technology (LIT), a low power, low cost audio processor for information dissemination among illiterate people groups in developing regions. The 265 K gate, 8 million transistor, 23 mm2, ARM Cortex M0 processor uses a novel memory hierarchy consisting of an on chip 128 kB true LRU cache and off-chip NAND Flash. LIT reduces initial acquisition cost through a high-level of integration that results in a low board-level component count. In addition, it also reduces recurring cost through design decisions that lower energy consumption. LIT's multiple power operational modes and power management schemes are specifically designed for efficient operation on Carbon Zinc batteries. These are commonly found in developing regions and allow LIT to be priced at a point that is viable for illiterate people groups in developing regions. View full abstract»

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  • Mixer-First FSK Receiver With Automatic Frequency Control for Body Area Networks

    Publication Year: 2013 , Page(s): 2051 - 2063
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    We present a low-power (382 ) body area network receiver operating in the 900 MHz band. The wideband FSK receiver supports bit rates up to 625 kbps. To save power, the power consuming phase-locked-loop (PLL) is replaced by an energy efficient digital automatic frequency control (AFC) loop. The AFC acts as a low-bandwidth frequency-locked-loop (FLL), using the FSK demodulator as frequency detector; the measured frequency offset is fed back to the on-chip digitally controlled oscillator. To further decrease the power consumption, the LNA is removed, the passive mixer being the first circuit in the receiver front-end. The mixer-first topology increases the linearity compared to injectionlocked and envelope detector based receivers. Additionally, analytical passive mixer transducer power gain and noise figure models are presented which are used to obtain an optimal mixer-first design. We achieve a -81 dBm sensitivity at a bit rate of 12.5 kbps. View full abstract»

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  • Design of a Self-Oscillating PWM Signal Generator With a Double Integration Loop

    Publication Year: 2013 , Page(s): 2064 - 2073
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1768 KB) |  | HTML iconHTML  

    A novel digital self-oscillating pulse width modulation (PWM) signal generator with a hysteresis comparator is proposed in this study. The proposed generator, referred to as a “2nd-order PWM signal generator” in this paper, utilizes a double integration loop based upon the concept of delta-sigma modulation for precise conversion. A simple 2nd-order PWM signal generator was initially investigated, but it was found to exhibit impractical behavior: the period of the PWM output signal increased slowly with time. An analysis of the limit cycle state of this simple generator using describing function theory shows that the amplitude of the limit cycle is extremely large. Proportional integral (PI) compensation is therefore used to adjust the limit cycle state by varying the proportional gain and the coefficient of the integral. The use of PI compensation suppresses the amplitude of the limit cycle, thus making the 2nd-order PWM signal generator practical. An analysis of this modified generator reveals that the period of the PWM signal can be controlled by the hysteresis width of the comparator and by the proportional gain. As a test case, a switching frequency of 300 kHz is used for the performance evaluation of the proposed PWM signal generator with a sampling frequency of 12.5 MHz. A noise-shaped output is obtained, and a high-precision, ultra-low-distortion PWM signal with a high effective duty cycle resolution is achieved. View full abstract»

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  • High Precision LC Ladder Synthesis Part I: Lowpass Ladder Synthesis via Parametric Approach

    Publication Year: 2013 , Page(s): 2074 - 2083
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2776 KB) |  | HTML iconHTML  

    In this paper, a novel, high precision lowpass LC ladder synthesis algorithm is presented. The new algorithm directly works on the driving point input immitance function which describes the lowpass LC ladder in resistive termination. The crux of the idea is that, at each step of the proposed method, a simple pole at infinity is removed then, the remaining immitance function is corrected using the parametric method. Parametric method warrants the exact lowpass LC ladder nature of the remaining immitance function. Thus, at the end of the synthesis process, a lowpass LC ladder is obtained with high numerical precision. Examples are presented to exhibit the implementation of the synthesis algorithm. A randomly generated driving point input immitance is synthesized with 19 elements yielding a relative error less than 10-6. Furthermore, numerical robustness of the novel synthesis method is tested. Based on the tests, we can confidently state that, proposed synthesis algorithm can safely extract more than 40 elements from the original immitance function with a relative error less than 10-2. Newly developed synthesis algorithm is coded on MatLab environment and it is successfully combined with the “Real Frequency-Direct Computational Technique” to construct practical impedance matching networks. View full abstract»

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  • Low-Voltage Bulk-Driven Operational Amplifier With Improved Transconductance

    Publication Year: 2013 , Page(s): 2084 - 2091
    Cited by:  Papers (2)
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    This paper presents two low-voltage bulk-driven amplifier input stages with enhanced transconductance. The idea is to introduce auxiliary differential pairs into a conventional bulk-driven stage to boost its transconductance. A low-voltage cascode biasing circuitry based on EKV models is also employed to ensure proper operation of the proposed input stages. An operational amplifier is then implemented with the proposed input stages and biasing circuits as its core building blocks and including a modified low-voltage class AB output amplifier to guarantee rail-to-rail output voltage range. The overall amplifier was implemented in a 0.35 μm n-well CMOS process using 1-V power supply. The measurement results show significant improvement in the performance of the operational amplifier compared to prior arts. View full abstract»

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  • An Improved High Linearity Active CMOS Mixer: Design and Volterra Series Analysis

    Publication Year: 2013 , Page(s): 2092 - 2103
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3461 KB) |  | HTML iconHTML  

    The linearity and noise requirements in multistandard applications make the design of mixers so challenging. In this paper a new highly linear CMOS mixer is proposed that utilizes second- and third-order distortion cancellation mechanisms using second harmonic injection technique, also an in-depth analysis of the mixer is presented too. The proposed circuit can work for wide channel bandwidth applications. Full Volterra series analysis of the transconductance stage of the proposed mixer is reported to show the effectiveness of the injection technique. The analysis of the mechanisms responsible for generating the fundamental tone, the second- and the third-order intermodulation distortions in the switching stage along with an LC filter is also reported. Simulations using TSMC 0.18 μm CMOS model technology demonstrate that IIP3 and IIP2 of the proposed mixer have 10 dB and 26 dB improvements in comparison with the conventional Gilbert-type mixer while the NF doesn't change significantly. The mixer achieves a conversion gain of 15 dB from a 1.8 V supply. The additional circuits used for the IM2 and IM3 cancellation mechanisms have a total current consumption of less than 1 mA. View full abstract»

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  • Phase Noise and Noise Induced Frequency Shift in Stochastic Nonlinear Oscillators

    Publication Year: 2013 , Page(s): 2104 - 2115
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2752 KB) |  | HTML iconHTML  

    Phase noise plays an important role in the performances of electronic oscillators. Traditional approaches describe the phase noise problem as a purely diffusive process. In this paper we develop a novel phase model reduction technique for phase noise analysis of nonlinear oscillators subject to stochastic inputs. We obtain analytical equations for both the phase deviation and the probability density function of the phase deviation. We show that, in general, the phase reduced models include non Markovian terms. Under the Markovian assumption, we demonstrate that the effect of white noise is to generate both phase diffusion and a frequency shift, i.e. phase noise is best described as a convection-diffusion process. The analysis of a solvable model shows the accuracy of our theory, and that it gives better predictions than traditional phase models. View full abstract»

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  • CMOS Tunable-Color Image Sensor With Dual-ADC Shot-Noise-Aware Dynamic Range Extension

    Publication Year: 2013 , Page(s): 2116 - 2129
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3031 KB) |  | HTML iconHTML  

    A wide dynamic range CMOS tunable-color image sensor is presented. The sensor integrates an 8 × 8 array of tunable-color photogates which exploit the wavelength-dependent optical absorption properties of the polysilicon gate structure. An analysis is presented for the wide dynamic range asynchronous self-reset with residue readout architecture where photon shot noise is taken into consideration. An implementation of this architecture is presented where the (coarse) asynchronous self-reset operation and (line) residue analog-to-digital conversions are performed with separate in-pixel and off-pixel circuits, respectively, for a noise-optimized design. A prototype was fabricated in a standard 0.35 μm CMOS process and is validated in color light sensing which achieves SNRs of 24.3 dB and 28.5 dB in green and red light measurements, respectively, under a moderate input light intensity of 300 μW/cm2. The readout circuit achieves a measured dynamic range of 82 dB with a peak SNR of 46.2 dB under broadband illumination. The prototype has been integrated with a microfluidic device and experimentally validated in fluorescence contact imaging. View full abstract»

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  • Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters

    Publication Year: 2013 , Page(s): 2130 - 2138
    Cited by:  Papers (2)
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    Highly digital-oriented architectures for sensor interfaces are very interesting for their high energy efficiency, especially in smaller CMOS technologies which offer low-voltage design. This paper presents the analysis of a Bang-Bang Phase-Locked Loop Sensor-to-Digital Converter (BBPLL SDC). The highly digital-oriented BBPLL offers advantages such as the low chip area, excellent scalability towards smaller technologies, robustness towards process variations and low-voltage possibilities, making this architecture very interesting for energy-efficient applications. Theoretical analysis of the structure shows that the BBPLL SDC resembles a -modulator with first-order quantization noise shaping due to the frequency-to-phase conversion of the oscillators. Oscillator phase noise however plays an important role in the analysis and limits the SNR in practical implementations. To validate the theoretical analysis, a state-variable-based non-linear Matlab model has been developed, including non-idealities such as phase noise, non-linearity and mismatch. Based on practically achievable phase noise values of state of the art oscillators, simulations show that resolutions up to 110 dB can be achieved. An estimation of the power consumption of the oscillators, based on state of the art figures, results in energy-efficient designs beyond the state of the art with moderate resolutions of 40-80 dB SNR, while high resolutions of 80-110 dB demand higher power consumption in the oscillators, resulting in designs with lower energy efficiency, but still competitive with the current state of the art. A design strategy for both an energy-efficient and a high-performance BBPLL SDC is provided. View full abstract»

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  • A New RNS based DA Approach for Inner Product Computation

    Publication Year: 2013 , Page(s): 2139 - 2152
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2516 KB) |  | HTML iconHTML  

    This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme. View full abstract»

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  • Statistical Characterization of Noise and Interference in NAND Flash Memory

    Publication Year: 2013 , Page(s): 2153 - 2164
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2479 KB) |  | HTML iconHTML  

    Given the limited set of empirical input/output data from flash memory cells, we describe a technique to statistically analyze different sources that cause the mean-shifts and random fluctuations in the read values of the cells. In particular, for a given victim cell, we are able to quantify the amount of interference coming from any arbitrarily chosen set of potentially influencing cells. The effect of noise and interference on the victim cell after repeated program/erase cycles as well as baking is also investigated. The results presented here can be used to construct a channel model with data-dependent noise and interference characteristics, which in turn can be utilized in designing and evaluating advanced coding and signal processing methods for flash memory. View full abstract»

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  • Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm

    Publication Year: 2013 , Page(s): 2165 - 2176
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    A dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architectural design of this work is different from the one of previous works that focus on the iterative clustering algorithm. The system includes a set of memories that operates in ping-pong mode, so that the Manhattan distances can be computed when the centroids are updated. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the computational time of one division operation to a single clock cycle and to calculate cumulative moving averages with no precision loss. Two hardware examples show the robustness of the proposed architecture, and the architectural analysis is performed with the 90 nm CMOS technology. In the first example, the gate count is the smallest and the normalized power consumption of this work is the lowest among previous works. In the second example, the architecture is compared with related works, which implement the Self-Organizing Map (SOM) algorithm. The proposed work has high flexibility for parameter combinations and can achieve high performance for color quantization in a single iteration. The functionalities of the proposed system are also verified with the background subtraction application. View full abstract»

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  • An Ultra Low-Power Solution for EEPROM in Passive UHF RFID Tag IC With a Novel Read Circuit and a Time-Divided Charge Pump

    Publication Year: 2013 , Page(s): 2177 - 2186
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    A dual power supply ultra low-power 1 kbits EEPROM for passive UHF RFID is presented. The read power source is 1 V, while the write power source is 1.65 V, which is only activated in the write mode. To reduce the power of the read circuit without impacting the performance, a pre-charge scheme, a feedback scheme and a self-detect circuit, combined with a special read time sequence are adopted. A time-divided charge pump is proposed to reduce the current surge of the charge pump at the startup phase. The EEPROM IP has been fabricated in a SMIC 0.18 μm 2P4M EEPROM process. The die size of the proposed EEPROM IP is 0.12 mm2. The read and write currents of the EEPROM IP are 1.18 μA and 33 μA respectively. Under a 110 temperature variation, the power variation of the read operation is 15%. The EEPROM IP is then verified in a full UHF RFID chip. Tested by a commercial reader at 4 W EIRP, the maximum read and write communication ranges are 6 m and 3 m respectively. The measured voltage drop of the output of rectifier Vrect caused by the current surge of the charge pump is smaller than 50 mV. View full abstract»

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  • Implications of I/Q Imbalance, Phase Noise and Noise Figure for SNR and BER of FSK Receivers

    Publication Year: 2013 , Page(s): 2187 - 2198
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2696 KB) |  | HTML iconHTML  

    In energy-constrained applications like Body Area Networks (BAN) receiver performance is traded for lower power consumption. The limited receiver performance will deteriorate the output signal-to-noise-ratio (SNR) and bit-error-rate (BER) of the receiver. In this paper we present closed-form output SNR and BER models of a non-ideal receiver front-end with limiter-discriminator demodulator for binary FSK. The presented model is very useful in defining the minimally required receiver specifications. Moreover, the models are useful for gaining insight into the influences of the receiver impairments on its performance. In the models, the gain and phase imbalances between the in-phase and quadrature-phase paths as well as the receiver generated noise and the phase noise produced by the local frequency reference are taken into account. This paper shows that the gain and phase imbalances shift the FM threshold to higher carrier-to-noise-ratios (CNR) and only have small influence on the SNR above threshold. On the other hand, receiver generated noise reduces the output SNR both below and above the FM threshold, and phase noise limits the maximum output SNR. Additionally, a trade-off between the FSK frequency deviation and phase noise robustness is derived. View full abstract»

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  • A Cost-Effective Preamble-Assisted Engine With Skew Calibrator for Frequency-Dependent I/Q Imbalance in 4x4 MIMO-OFDM Modem

    Publication Year: 2013 , Page(s): 2199 - 2212
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6227 KB) |  | HTML iconHTML  

    Variations in I/Q gains, phases, and filters of the RF frontend, namely frequency-dependent I/Q imbalance (FDI), are an important factor in OFDM-based wireless access. To enable the proper function of a 4 × 4 MIMO-OFDM receiver this work proposes a low-complexity preamble-assisted solution using only one complex divider and one complex multiplier to handle significant FDI distortions. An all-digital multiphase and multi-rate clock generator (MPRCG) was built to support fast dynamic frequency scaling for FDI estimation and compensation and for efficient implementation. Based on the proposed MPRCG, a skew calibration was also realized to tune I/Q timing coherently via multiphase A/D clocking. Performance evaluation showed that the proposed approach incurs an SNR loss of 1.5 dB to maintain a packet-error rate of less than 10% under a 1 dB gain error, 15 phase error and worse filter mismatch. Thus, this solution not only provides adequate performance, but also makes FDI estimation and compensation more cost-effective. View full abstract»

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  • A 100 MHz Two-Phase Four-Segment DC-DC Converter With Light Load Efficiency Enhancement in 0.18/spl mu/m CMOS

    Publication Year: 2013 , Page(s): 2213 - 2224
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2255 KB) |  | HTML iconHTML  

    This paper describes a high switching frequency CMOS DC-DC converter employing phase shedding/segmentation and resonant gate drivers to improve light load efficiency. A novel output inductor network with positively coupled inductors between segments and negatively coupled inductors between phases is adopted in two-phase four-segment interleaved topology to improve effective inductance and reduce inductor current ripple. To limit the contribution of the gate driver to the total converter loss under light and medium loads, a new combined high-side and low-side resonant type gate driver with partially shared inductor is presented. The DC-DC converter is implemented in 0.18 μm six-metal CMOS technology with 5 V power devices and occupies a total area of 2.55 mm × 3.0 mm. It converts 4 V input to 1 to 3 V output with peak 1.78 A current under 100 MHz switching frequency. The measured peak efficiency is 77.4% at 5.95 W output power and the tracking mode bandwidth can reach up to 8 MHz. With resonant gate drivers, 5% efficiency improvement can be reached at 1 V output. Furthermore, the converter is able to maintain peak efficiency as the output current varies from 0.1 A to 1.86 A. View full abstract»

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The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras