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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 7 • Date July 2013

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Displaying Results 1 - 25 of 31
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems - I: Regular Papers publication information

    Publication Year: 2013 , Page(s): C2
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  • A Three-State Signal Coding Scheme for High Efficiency Class-S Amplifiers

    Publication Year: 2013 , Page(s): 1681 - 1691
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1798 KB) |  | HTML iconHTML  

    A three-state signal coding scheme is proposed for driving Class-S amplifiers with higher efficiency than conventional techniques. The approach is formulated in the framework of polar modulation, where the magnitude is controlled by a timing code that specifies positive and negative rectangular pulses as well as a third zero state, and the phase is varied by modulating the clock delay. In particular, high efficiency is attained when the active pulse widths are a half-cycle of the carrier frequency, and the zero-state is formed by skipping pulses. In this case, full-amplitude modulation has the same efficiency as a Class-D amplifier, and is only slightly degraded as the amplitude is decreased. In addition, the technique operates at only 2X sampling and is very simple to implement. Spectral analysis is performed for baseband signals consisting of single tones, 2-tone suppressed-carrier, and bandlimited random noise. The latter case emulates real communication signals and is shown to exhibit good spectral characteristics and low error-vector magnitude in the time domain. An important application of this technique is in all-digital, power-efficient power amplifiers for cellular base stations and handsets. View full abstract»

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  • A 0.007-mm2 108- {\rm p\pm}/^{\circ } {\rm C} 1-MHz Relaxation Oscillator for High-Temperature Applications up to 180 ^{\circ } {\rm C} in 0.13- \mu {\rm m} CMOS

    Publication Year: 2013 , Page(s): 1692 - 1701
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1853 KB) |  | HTML iconHTML  

    Reliable high-temperature CMOS oscillators are required for clock or time-base generation in several applications including data acquisition for aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In this paper, we present low-complexity resistive and capacitive temperature-compensation techniques for CMOS relaxation oscillators. In such oscillators, the frequency of oscillation is a function of a resistor-capacitor product. The resistive compensation technique employs a recently proposed monolithic resistor with a given temperature coefficient (TC) that uses contacts to adjust the TC of the resistor. The capacitive compensation technique is based on using a varactor to adjust the value of the timing capacitance over temperature to compensate for the high-temperature junction leakage current and to keep the oscillation frequency relatively constant. A prototype oscillator based on the proposed techniques is implemented in a standard 0.13-μm CMOS process and reliably operates over 25 to 180 °C. Measured results show that over the temperature range of interest the compensated oscillator achieves a temperature coefficient of 108 ppm/°C. The oscillator along with its output drivers occupies 7200 μm2 (2.3 × to 114 × smaller than state-of-the-art designs) and consumes 428 μW from a 2.5 V supply. For supply variations between 2 and 3 V, the frequency variation is ±1.09%/V. View full abstract»

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  • A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications

    Publication Year: 2013 , Page(s): 1702 - 1711
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1854 KB) |  | HTML iconHTML  

    In typical direct radio frequency (RF) sampling receivers, the sample clock jitter results in SNR degradation on received signals that increases log linearly with RF signal frequency. De-jittering received signals is computationally expensive, especially for wideband communications signals, because the induced jitter on received signals varies as a function of RF signal frequency. This paper considers a reconfigurable direct RF receiver (RDRFR) that has a stair-step jitter pattern as a function of RF signal frequency. The RDRFR uses a two-stage sampling circuit. In the first stage, the RF input is bandpass filtered and pulse sampled without quantizing the signal. The discrete-time analog signal is then interpolated with a continuous time low-pass filter, then sampled and quantized by a traditional analog-to-digital converter. With this two-stage sampling circuit, the induced signal jitter from the RF sampling is identical for all in-band signals and is the same to within an integer scale factor for all signals, in-band or out-of-band. This key circuit property means that it is possible to remove jitter with very low computational complexity in the RDRFR. Furthermore, this result can be exploited to improve system performance with non-ideal anti-alias filters by identifying non-desired signals caused by out-of-band leakage. View full abstract»

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  • Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators

    Publication Year: 2013 , Page(s): 1712 - 1725
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3845 KB) |  | HTML iconHTML  

    Frequency dividers can be modeled as superharmonic injection-locked oscillators. We propose a general model for ring-oscillator based dividers. Theoretically, the maximum division frequency of a frequency divider can be decoupled from the number of phases at its output when multipath coupling of ring oscillators is used. Accurate expressions for the locking range are derived that are used to find the optimum structure to maximize the division frequency. The results of the model are incorporated into a design procedure that can rapidly explore various coupling and sizing of the multipath structure. A design of a divider chain for a 48-Gb/s serializing transmitter is used as a demonstration. View full abstract»

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  • An 8-Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a Counter-Based Digital Control Circuitry

    Publication Year: 2013 , Page(s): 1726 - 1739
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2794 KB) |  | HTML iconHTML  

    This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency biosensor applications. Two new techniques are introduced: 1) a novel digital-to-analog converter (DAC) switching method suitable for single-ended SAR ADCs; and 2) a counter-based digital control circuitry. The DAC switching method uses VR/2 as an only reference voltage to digitize the input signals within [0, VR ], and reduces the power consumption in the DAC during digitizing by 87.5% versus the traditional one. The counter-based controller can reduce power consumption in the digital circuitry by 30%. Two prototype 8-bit SAR ADCs are designed, one in a TI 0.35-μm Bipolar-CMOS-DMOS (BCD) process and the other in a TSMC 0.18-μm CMOS process. The 0.35-μm ADC consumes 101 nW, and achieves a signal to noise and distortion ratio (SNDR) of 48.2 dB and a figure of merit (FOM) of 227 fJ/conversion-step at 2 kS/s. The 0.18-μm ADC can achieve a SNDR of 46.3 dB with only 27 nW and a FOM of 79.9 fJ/conversion-step at 2 kS/s. View full abstract»

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  • A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators

    Publication Year: 2013 , Page(s): 1740 - 1752
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    Just as their single-bit counterparts, multi-bit sigma delta modulators exhibit nonlinear behavior due to the presence of the quantizer in the loop. In the multi-bit case this is caused by the fact that any quantizer has a limited output range and hence gives an implicit saturation effect. Due to this, any multi-bit modulator is prone to modulator overloading. Unfortunately, until now, designers had to rely on extensive time-domain simulations to predict the overloading level, because there is no adequate analytical theory to model this effect. View full abstract»

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  • Design of CML Ring Oscillators With Low Supply Sensitivity

    Publication Year: 2013 , Page(s): 1753 - 1763
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2386 KB) |  | HTML iconHTML  

    The causes of supply noise-induced frequency variation in CML ring oscillators are investigated and a novel circuit topology that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum oscillation frequency and maintains nearly the same random jitter generation while greatly reducing the sinusoidal jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18 μm CMOS process verify the effectiveness of the proposed technique. View full abstract»

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  • Energy Efficient Low-Noise Multichannel Neural Amplifier in Submicron CMOS Process

    Publication Year: 2013 , Page(s): 1764 - 1775
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2292 KB) |  | HTML iconHTML  

    This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channel's input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 μW of power, while its input referred noise is equal to 4.4 μV resulting in NEF equal to 4.1. View full abstract»

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  • Oscillator Instability Effects in Time Interval Measurement

    Publication Year: 2013 , Page(s): 1776 - 1786
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1627 KB) |  | HTML iconHTML  

    State-of-the-art TDCs can have a precision close to one picosecond, for which reason clock instability is starting to be one of the most significant factor limiting the precision. This paper provides methods to estimate clock jitter induced error by phase noise PSD measurements. Due to the different noise processes of the power-law model, convergence problems might restrict the time domain conversion of clock instabilities. Since time interval measurement corresponds to measuring the first difference of phase error, the convergence problems cannot be completely avoided as is usually done when characterizing frequency instabilities in time domain by measuring the 2nd differences of the phase error. This issue is addressed by taking into account the finite observation window of the phase error. Also a simple PSD measurement technique is introduced to provide an estimate of the jitter due to noise floor with an unknown bandwidth. Spurious tones in the phase noise PSD are also shown to have a significant impact on the precision of a TDC. The results are confirmed by several measurements done with a time-to-digital converter having a 1-ps precision. View full abstract»

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  • A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration

    Publication Year: 2013 , Page(s): 1787 - 1799
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2972 KB) |  | HTML iconHTML  

    This paper describes a calibration technique for noisy and nonconvex circuit responses based on the Nelder-Mead direct search algorithm. As Nelder-Mead is intended for unconstrained optimization problems, we present an implementation of the algorithm which is suitable for bounded and discretized RFIC calibration problems. We apply the proposed algorithm to the problem of spurious tone reduction via VCO control line ripple minimization for a PLL operating at a frequency of 12 GHz. For this nonconvex calibration test case, we show that a gradient descent-based algorithm has difficulty in reducing the VCO control line ripple, while the proposed algorithm reduces the relative power of the first harmonic reference spurs by at least 10 dBc and effectively enables design complexity reduction in the supporting analog calibration circuitry. View full abstract»

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  • A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels

    Publication Year: 2013 , Page(s): 1800 - 1809
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2348 KB) |  | HTML iconHTML  

    Delta-Integration, a novel readout method, is introduced in an effort to solve the noise and speed issues impeding the performance of in-cell touch screen panels. In the proposed method, a differential sensing scheme effectively cancels common noise components and locally occurring noise is spatially low-pass filtered. Due to the consequently enhanced Signal- to-Noise Ratio, the proposed scheme is simply implemented by a comparator and a counter only in place of a complex ADC. The comparator is designed to have a `dead-zone' for noise-immune characteristics. In addition, a new global charge amplifier that has much wider bandwidth and higher current-driving capability than the conventional one is proposed for high speed operation. The prototype chip consumes a static power of 1.15 mW and the total chip area without panel loads is 2.5 mm2. View full abstract»

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  • A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 /spl mu/m CMOS Process

    Publication Year: 2013 , Page(s): 1810 - 1822
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2419 KB) |  | HTML iconHTML  

    We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively. View full abstract»

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  • Moving Horizon Estimation for Networked Systems With Quantized Measurements and Packet Dropouts

    Publication Year: 2013 , Page(s): 1823 - 1834
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3008 KB) |  | HTML iconHTML  

    This paper is concerned with the moving horizon estimation (MHE) problem for linear discrete-time systems with limited communication, including quantized measurements and packet dropouts. The measured output is quantized by a logarithmic quantizer and the packet dropout phenomena is modeled by a binary switching random sequence. The main purpose of this paper is to design an estimator such that, for all possible quantized errors and packet dropouts, the state estimation error sequence is convergent. By choosing a stochastic cost function, the optimal estimator is obtained by solving a regularized least-squares problem with uncertain parameters. The proposed method can be used to deal with the estimation and prediction problems for systems with quantized errors and packet dropouts in a unified framework. The stability properties of the optimal estimator are also studied. The obtained stability condition implicitly establishes a relation between the upper bound of the estimation error and two parameters, namely, the quantization density and the packet dropout probability. Moreover, the maximum quantization density and the maximum packet dropout probability are given to ensure the convergence of the upper bound of the estimation error sequence. Finally, an illustrative example is given to demonstrate the effectiveness of the proposed method. View full abstract»

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  • Fast Time-Recursive Block Correlators for Pseudorandom Sequences

    Publication Year: 2013 , Page(s): 1835 - 1844
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    Correlators for pseudorandom sequences are used in direct sequence spread spectrum communication systems for signal synchronization and identification of transmitters. Implementation aspects of these correlators are critical for real-time processing of signals. This paper presents fast correlator structures in time domain which significantly reduce redundant operations using time-recursive and block processing. The approach can be extended to other applications which use correlations with both binary and non-binary sequences. View full abstract»

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  • Low-Complexity Maximally-Decimated Multirate 3-D Spatio-Temporal FIR Cone and Frustum Filters

    Publication Year: 2013 , Page(s): 1845 - 1856
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2755 KB) |  | HTML iconHTML  

    A low-complexity multirate 3-D spatio-temporal FIR cone and frustum filter structure is proposed having potential applications as a spatio-temporal directional filter. The cone filter structure employs a 1-D modified discrete Fourier transform (DFT) filter bank and 2-D spatial filters. The frustum filter having a double-frustum-shaped passband oriented along the temporal frequency axis is approximated by employing an appropriate subset of subbands. Low computational complexity is achieved by maximal decimation in the temporal dimension, and by employing the DFT-polyphase realization to implement the 1-D modified DFT filter bank. The cone and frustum filters are almost alias free, and provide near-perfect reconstruction. The reduction in computational complexity, relative to undecimated and under-decimated realizations, is numerically confirmed by means of a potential application involving the attenuation of strong broadband plane wave interference. View full abstract»

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  • A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

    Publication Year: 2013 , Page(s): 1857 - 1869
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2920 KB) |  | HTML iconHTML  

    This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise power-spectral-density ratio (Eb/N0) of 3.55 dB. View full abstract»

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  • Probe Based Shooting Method to Find Stable and Unstable Limit Cycles of Strongly Nonlinear High-q Oscillators

    Publication Year: 2013 , Page(s): 1870 - 1880
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2293 KB) |  | HTML iconHTML  

    Probe insertion technique is considered as an exclusively frequency domain approach. It has been developed to increase robustness of the harmonic balance method, when simulating autonomous circuits to avoid the dc degenerate solution. This technique evidences several good properties, for instance when simulating oscillators either employing high quality factor resonators or ac coupled ones. In this paper the probe insertion technique is extended to the time domain. This allows the application of the shooting method to a wider class of circuits including for example crystal oscillators. The inherent superiority of the shooting method to simulate strongly nonlinear circuits and its recent reliable extension to mixed analog/digital ones outperforms the potentiality of the harmonic balance method. Furthermore, this time domain probe insertion technique is exploited to find possible multiple steady state solutions and efficiently check stability properties, thus avoiding to compute the eigenvalues of the monodromy matrix. View full abstract»

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  • Semi-Global Leader-Following Consensus of Linear Multi-Agent Systems With Input Saturation via Low Gain Feedback

    Publication Year: 2013 , Page(s): 1881 - 1889
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2619 KB) |  | HTML iconHTML  

    This paper investigates the problem of leader-following consensus of a linear multi-agent system on a switching network. The input of each agent is subject to saturation. Low gain feedback based distributed consensus protocols are developed. It is established that, under the assumptions that each agent is asymptotically null controllable with bounded controls and that the network is connected or jointly connected, semi-global leader-following consensus of the multi-agent system can be achieved. Numerical examples are presented to illustrate this result. View full abstract»

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  • A Multiobjective Approach for Source Estimation in Fuzzy Networked Systems

    Publication Year: 2013 , Page(s): 1890 - 1900
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3571 KB) |  | HTML iconHTML  

    In this paper, fuzzy networked systems with a randomly varying delay and quantization errors are considered to represent signal transmission systems of nonlinearly interactive sources. A source estimation scheme is proposed by using a multiobjective approach, addressing the concerns of estimation errors and transmission power consumption. A mixed H2/H design is employed to enhance the estimation performance, while the number of quantized bits is optimized to reduce the power consumption. A Pareto front representation is adopted so that the proposed estimation scheme is designed from a broader perspective in contrast with the conventional single-objective approach. It turns out that the proposed source estimator parameters can serve as decision variables of a multiobjective optimization problem (MOP) with linear matrix inequality constraints. This MOP can be solved by using deterministic algorithms, such as interior-point methods, for solutions of internal variables and using stochastic algorithms, such as multiobjective evolutionary algorithms, for the global optimality. Numerical examples are provided to illustrate the proposed methodology. View full abstract»

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  • Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters

    Publication Year: 2013 , Page(s): 1901 - 1914
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3128 KB) |  | HTML iconHTML  

    The utilization of a burst-mode power amplifier (PA) together with pulse-width modulation (PWM) is a promising concept for achieving high efficiency in radio frequency (RF) transmitters. Nevertheless, such a transmitter architecture requires bandpass filtering to suppress side-band spectral components to retrieve the wanted signal, which reduces the transmit power and the transmitter efficiency. High efficiency can only be expected with the maximum transmit power and signals with low peak-to-average-power ratios (PAPRs). To boost efficiency for signals with high PAPRs and signals at variable transmit power levels, the burst-mode multilevel transmitter architecture has been widely discussed as a potential solution. This paper presents an efficiency optimization procedure of burst-mode multilevel transmitters for signals with high PAPRs and signals at variable transmit power levels. The impact of the threshold value on the transmitter efficiency is studied, where the optimum threshold value and the maximum transmitter efficiency can be obtained according to input magnitude statistics. In addition, the relation between the threshold value and the efficiency expression of burst-mode multilevel transmitters and those of Doherty PAs is investigated. It is shown that the obtained optimum threshold value, although originally designed for burst-mode transmitters, can also be applied to Doherty and multistage Doherty PAs to achieve maximum transmitter efficiency. Simulations are used to validate the efficiency improvement of the optimized burst-mode multilevel transmitters compared to two-level and non-optimized multilevel transmitters. View full abstract»

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  • Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS

    Publication Year: 2013 , Page(s): 1915 - 1928
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2968 KB) |  | HTML iconHTML  

    This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the model estimation problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluated for 5 MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to one of the first fully integrated +30 dBm Class-D outphasing RF PAs in 65 nm CMOS. At 1.95 GHz for a 5.5 V (6.0 V) supply voltage, the measured output power of the PA was +29.7 dBm (+30.5 dBm) with a power-added efficiency (PAE) of 27%. For the WCDMA signal with +26.0 dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5 MHz and 10 MHz offsets were - 46.3 dBc and - 55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3 dBm of channel power, the measured ACLR at 5 MHz offset was - 43.5 dBc with predistortion, compared to -34.1 dBc without predistortion. View full abstract»

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  • Optical Receiver Using Noise Cancelling With an Integrated Photodiode in 40 nm CMOS Technology

    Publication Year: 2013 , Page(s): 1929 - 1936
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1670 KB) |  | HTML iconHTML  

    A transimpedance amplifier (TIA) based on an inverting voltage amplifier with a shunt feedback resistor using a noise cancelling technique is presented. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 Ω differential output driver to provide an interface to the measurement setup. The TIA shows a measured optical sensitivity of -20.7 dBm for a BER of 10-9 using an external photodiode (PD). Another chip with the same TIA and an integrated N+/Psub PD is also introduced. The optical receiver achieves a measured transimpedance gain of 78 dBΩ, 1.5 GHz bandwidth and a measured input referred noise current density of 7.2 pA/√Hz up to 1.5 GHz. The power consumption of the TIA is only 4.1 mW and the complete chip dissipates 12 mW for a single 1 V supply voltage. View full abstract»

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  • A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems

    Publication Year: 2013 , Page(s): 1937 - 1945
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    This work investigates the improvement of power amplifier efficiency through the reduction of peak-to-average power ratio (PAPR) of linearly precoded QAM data signals. In particular, we focus on the special cases of linear precoded modulation including the practical OFDM, OFDMA, and SC-FDMA signals that have been widely adopted in W-LAN and W-MAN. We apply the method of tone injection optimization for PAPR reduction. To reduce numerical complexity, we propose a linear programming algorithm which closely approximates the original tone injection optimization problem. Our comprehensive numerical results demonstrate substantial PAPR reduction and superior BER performance using several practical examples. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras