# IEEE Transactions on Circuits and Systems I: Regular Papers

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Displaying Results 1 - 25 of 32

Publication Year: 2013, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems - I: Regular Papers publication information

Publication Year: 2013, Page(s): C2
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• ### Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation

Publication Year: 2013, Page(s):1369 - 1380
Cited by:  Papers (4)
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The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is pro... View full abstract»

• ### Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

Publication Year: 2013, Page(s):1381 - 1394
Cited by:  Papers (16)
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This paper describes an accurate, yet analytical method to predict the key characteristics of a bang-bang controlled timing loop: namely, the jitter transfer (JTRAN), jitter generation (JG), and jitter tolerance (JTOL). The analysis basically derives a linearized model of the system, where the bang-bang phase detector is modeled as a set of two linearized gain elements and an additive white noise ... View full abstract»

• ### Frequency-Domain Study of Lock Range of Non-Harmonic Oscillators With Multiple Multi-Tone Injections

Publication Year: 2013, Page(s):1395 - 1406
Cited by:  Papers (4)
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This paper presents a frequency-domain study of the lock range of non-harmonic oscillators with multiple multi-tone injections. By representing non-harmonic oscillators with a set of harmonic oscillators, the intrinsic relation between the lock range of harmonic oscillators and that of non-harmonic oscillators is obtained. We show non-harmonic oscillators with a multi-tone injection exhibit a larg... View full abstract»

• ### Continuous Time Level Crossing Sampling ADC for Bio-Potential Recording Systems

Publication Year: 2013, Page(s):1407 - 1418
Cited by:  Papers (33)
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In this paper we present a fixed window level crossing sampling analog to digital convertor for bio-potential recording sensors. This is the first proposed and fully implemented fixed window level crossing ADC without local DACs and clocks. The circuit is designed to reduce data size, power, and silicon area in future wireless neurophysiological sensor systems. We built a testing system to measure... View full abstract»

• ### A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

Publication Year: 2013, Page(s):1419 - 1431
Cited by:  Papers (31)
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A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subs... View full abstract»

• ### On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2$\,\times\,$VDD Output Buffers

Publication Year: 2013, Page(s):1432 - 1440
Cited by:  Papers (7)
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A novel process and temperature compensation design for 2 VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2 × VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 μm CMOS process. By adjusting output currents, the slew rate of outp... View full abstract»

• ### VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

Publication Year: 2013, Page(s):1441 - 1454
Cited by:  Papers (34)
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Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel c... View full abstract»

• ### VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

Publication Year: 2013, Page(s):1455 - 1468
Cited by:  Papers (6)
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This paper proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4 and -6 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures employing parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architecture. It also guarantees a noise-free comp... View full abstract»

• ### Magnetic Adder Based on Racetrack Memory

Publication Year: 2013, Page(s):1469 - 1477
Cited by:  Papers (42)
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The miniaturization of integrated circuits based on complementary metal oxide semiconductor (CMOS) technology meets a significant slowdown in this decade due to several technological and scientific difficulties. Spintronic devices such as magnetic tunnel junction (MTJ) nanopillar become one of the most promising candidates for the next generation of memory and logic chips thanks to their non-volat... View full abstract»

• ### Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating

Publication Year: 2013, Page(s):1478 - 1486
Cited by:  Papers (14)
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Ternary content-addressable memory (TCAM) is a popular hardware device for fast routing lookup and an attractive solution for applications such as packet forwarding and classification. However, the high cost and power consumption are limiting its popularity and versatility. In this paper, a low leakage power TCAM architecture which uses two-side self power gating technique is proposed to reduce th... View full abstract»

• ### RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to$(8n+1)$-bit

Publication Year: 2013, Page(s):1487 - 1500
Cited by:  Papers (26)
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In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2n,2n-1,2n+1,2n-2(n+1)/2+1,2n+2(n+1)/2+1} , with an equivalent 5n-bit dynamic range, and propose horizontal and vertical extensions in order to improve the para... View full abstract»

• ### Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits

Publication Year: 2013, Page(s):1501 - 1510
Cited by:  Papers (1)
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Ultra-low-voltage operation can greatly reduce the power consumption of circuits. However, there is no fast, effective, and comprehensive technique for designers to estimate power, delay, or effects of process variation of a design operating in the ultra-low-voltage region. This paper presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage to the... View full abstract»

• ### An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells

Publication Year: 2013, Page(s):1511 - 1520
Cited by:  Papers (12)
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To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel metho... View full abstract»

• ### A 256-Mcell Phase-Change Memory Chip Operating at$2{+}$Bit/Cell

Publication Year: 2013, Page(s):1521 - 1533
Cited by:  Papers (15)
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A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled... View full abstract»

• ### A Novel STT-MRAM Cell With Disturbance-Free Read Operation

Publication Year: 2013, Page(s):1534 - 1547
Cited by:  Papers (17)
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This paper presents a three-terminal Magnetic Tunnel Junction (MTJ) and its associated two transistor cell structure for use as a Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM) cell. The proposed cell is shown to have guaranteed read-disturbance immunity; during a read operation, the net torque acting on the storage cell always acts in a direction to refresh the data stored ... View full abstract»

• ### New Improved Recursive Least-Squares Adaptive-Filtering Algorithms

Publication Year: 2013, Page(s):1548 - 1558
Cited by:  Papers (23)
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Two new improved recursive least-squares adaptive-filtering algorithms, one with a variable forgetting factor and the other with a variable convergence factor are proposed. Optimal forgetting and convergence factors are obtained by minimizing the mean square of the noise-free a posteriori error signal. The determination of the optimal forgetting and convergence factors requires information about t... View full abstract»

• ### An Adaptive Subsystem Based Algorithm for Channel Equalization in a SIMO System

Publication Year: 2013, Page(s):1559 - 1569
Cited by:  Papers (1)
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The principle of multiple input/output inversion theorem (MINT) has been employed for multi-channel equalization. In this work, we propose to partition a single-input multiple-output system into two subsystems. The equivalence between the deconvoluted signals of the two subsystems is termed as auto-relation and we subsequently exploit this relation as an additional constraint to the existing adapt... View full abstract»

• ### First Order Mem-Circuits: Modeling, Nonlinear Oscillations and Bifurcations

Publication Year: 2013, Page(s):1570 - 1583
Cited by:  Papers (21)
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This paper presents a theoretical framework intended to accommodate circuit devices described by characteristics involving more than two fundamental variables. This framework is motivated by the recent appearance of a variety of so-called mem-devices in circuit theory, and makes it possible to model the coexistence of memory effects of different nature in a single device. With a compact formalism,... View full abstract»

• ### Digital Predistorter Design Using B-Spline Neural Network and Inverse of De Boor Algorithm

Publication Year: 2013, Page(s):1584 - 1594
Cited by:  Papers (14)  |  Patents (1)
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This contribution introduces a new digital predistorter to compensate serious distortions caused by memory high power amplifiers (HPAs) which exhibit output saturation characteristics. The proposed design is based on direct learning using a data-driven B-spline Wiener system modeling approach. The nonlinear HPA with memory is first identified based on the B-spline neural network model using the Ga... View full abstract»

• ### Second-Order Consensus Seeking in Multi-Agent Systems With Nonlinear Dynamics Over Random Switching Directed Networks

Publication Year: 2013, Page(s):1595 - 1607
Cited by:  Papers (71)
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This paper discusses the second-order local consensus problem for multi-agent systems with nonlinear dynamics over dynamically switching random directed networks. By applying the orthogonal decomposition method, the state vector of resulted error dynamical system can be decomposed as two transversal components, one of which evolves along the consensus manifold and the other evolves transversally w... View full abstract»

• ### Mitigation of Reverse Intermodulation Products at Colocated Base Stations

Publication Year: 2013, Page(s):1608 - 1620
Cited by:  Papers (5)
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In a co-located setting, large jamming signals from one transmitter can radiate into the antenna system of a second transmitter. The signals enter the second transmitter in the reverse direction and mix in the output stage of its power amplifier to produce intermodulation products. These `reverse' intermodulation products get radiated from the antenna system and may fall on the victim receiver's d... View full abstract»

• ### A Study on Multi-Level PWM and Asynchronous /spl Sigma/ /spl Delta/ Modulations for Enhanced Bandlimited Signal Tracking in Switching Power Amplifiers

Publication Year: 2013, Page(s):1621 - 1634
Cited by:  Papers (1)
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This work deals with multi-level switching amplifiers, in the context of high-efficiency power amplification for signal tracking applications. In particular, this paper evaluates the reduction in the error signal's power due to multi-level power amplification (compared to conventional two-level amplifiers) and compares the performance of two multi-level pulse modulations: PWM and Asynchronous ΣΔ M... View full abstract»

• ### Multi-Band Frequency Transformations, Matching Networks and Amplifiers

Publication Year: 2013, Page(s):1635 - 1647
Cited by:  Papers (32)
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In this paper, a technique for the synthesis of lumped element multi-band matching networks is proposed using frequency transformations. The proposed technique has been generalized forn-bands using 1→nfrequency transformations. The effect of the transformations on the bandwidth of the matching network and the effect of inductor losses on the transducer loss of the matching network ar... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK