IEEE Transactions on Circuits and Systems I: Regular Papers

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Publication Year: 2013, Page(s):C1 - C4
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• IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2013, Page(s): C2
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• Guest Editorial: Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012)

Publication Year: 2013, Page(s):1101 - 1103
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• A Subthreshold-MOSFETs-Based Scattered Relative Temperature Sensor Front-End With a Non-Calibrated $pm 2.5^{circ}{rm C}$ $3sigma$ Relative Inaccuracy From -$40^{circ}{rm C}$ to 100$^{circ}{rm C}$

Publication Year: 2013, Page(s):1104 - 1112
Cited by:  Papers (17)
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This paper presents a subthreshold MOSFETs-based scattered relative temperature sensor front-end operating at a low supply voltage. Dynamic element matching and dynamic offset cancellation have been implemented to minimize the errors induced by device mismatches. An individual proportional-to-absolute-temperature (PTAT) voltage generator was first implemented to verify the low voltage operation ca... View full abstract»

• All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal

Publication Year: 2013, Page(s):1113 - 1121
Cited by:  Papers (29)
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A new digital background calibration technique for gain mismatches and sample-time mismatches in a Time-Interleaved Analog-to-Digital Converter (TI-ADC) is presented to reduce the circuit area. In the proposed technique, the gain mismatches and the sample-time mismatches are calibrated by using pseudo aliasing signals instead of using a bank of adaptive FIR filters which is conventionally utilized... View full abstract»

• Low-Distortion Sine Wave Generation Using a Novel Harmonic Cancellation Technique

Publication Year: 2013, Page(s):1122 - 1134
Cited by:  Papers (18)
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A novel technique is proposed to generate robust, low distortion sine waves. In this method, outputs of a phase shift oscillator (PSO) are weighted and summed to obtain multiple outputs with very low distortion and precise phase relationship. The method allows a programmable number of harmonic distortion components to be cancelled over a wide frequency range. This work derives the condition for th... View full abstract»

• A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core

Publication Year: 2013, Page(s):1135 - 1148
Cited by:  Papers (24)
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This paper presents the design and implementation of an analog-to-information converter (AIC) capable of Nyquist and compressed sensing modes of operation. The core of the AIC is a 10-bit edge-triggered charge-sharing SAR ADC with a figure of merit (FOM) of 55 fJ/conversion-step and Nyquist-sampling rate of 9.5 Msample/s. The integration of a pseudorandom clock generator enables compressed sensing... View full abstract»

• Chopper-Stabilized Bidirectional Current Acquisition Circuits for Electrochemical Amperometric Biosensors

Publication Year: 2013, Page(s):1149 - 1157
Cited by:  Papers (18)  |  Patents (1)
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Two low-noise bidirectional current acquisition circuits for interfacing with electrochemical amperometric biosensor arrays are presented. The first design is a switched-capacitor transimpedance amplifier (TIA). The second design is a current conveyer (CC) with regulated-cascode current mirrors. Both circuits employ chopper stabilization to reduce flicker noise. The TIA and the CC were prototyped ... View full abstract»

• A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

Publication Year: 2013, Page(s):1158 - 1167
Cited by:  Papers (32)
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A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 �... View full abstract»

• Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier

Publication Year: 2013, Page(s):1168 - 1174
Cited by:  Papers (8)
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This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) for use in switched-capacitor (SC) circuits. Existing design methods for three-stage OTAs often lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal desig... View full abstract»

• Near Field Resonator Isolation System: Theory to Implementation

Publication Year: 2013, Page(s):1175 - 1187
Cited by:  Papers (3)
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The absence of electromagnetic wave motivates various studies of new communication channels in near field regime. An approach studied here is based on resonant inductive coupling and the use of Resonator Isolation (RI) system. The main concept of the RI system is to physically isolate two inductively coupled resonators from the signal input/output components. The resonators are charged with initia... View full abstract»

• A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme

Publication Year: 2013, Page(s):1188 - 1199
Cited by:  Papers (18)
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This paper presents a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying (GFSK) based transceiver suitable for wireless sensor network (WSN) applications. We propose several new techniques for lowering the power consumption in the frequency synthesizer. Resistor-based electro-static discharge protecti... View full abstract»

• A 37.5 /spl mu/W Body Channel Communication Wake-Up Receiver With Injection-Locking Ring Oscillator for Wireless Body Area Network

Publication Year: 2013, Page(s):1200 - 1208
Cited by:  Papers (21)
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An ultra-low power wake-up receiver for body channel communication (BCC) is implemented in 130 nm CMOS process. The proposed wake-up receiver uses the injection-locking ring oscillator (ILRO) to replace the RF amplifier with low power consumption. Through the ILRO, the frequency modulated input signal is amplified to the full swing rectangular signal directly demodulated by the following low power... View full abstract»

• A Multi-Band Low-Noise Transmitter With Digital Carrier Leakage Suppression and Linearity Enhancement

Publication Year: 2013, Page(s):1209 - 1219
Cited by:  Papers (5)
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A low-noise multi-band transmitter for GSM quad-band and WCDMA is presented. Programmable parameters of the analog baseband and the RF frontend enable adaption for different protocols and frequency bands. A three-step carrier leakage calibration algorithm is proposed to suppress the leakage to -65 dBm at highest RF gain. Novel linearization methods are used in the low-pass filter and the driver po... View full abstract»

• A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications

Publication Year: 2013, Page(s):1220 - 1231
Cited by:  Papers (4)
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This paper presents the theoretical analysis and simulation results of an IF to DC subsampler for 60 GHz heterodyne receivers architectures. A particular arrangement of the frequency plan allows embedded anti-alias filtering. Down-conversion, channel filtering and IQ demodulation are merged into a unique operation at no extra cost in terms of area and power consumption. The adjacent and alternate ... View full abstract»

• On-Chip Digital Inductor Current Sensor for Monolithic Digitally Controlled DC-DC Converter

Publication Year: 2013, Page(s):1232 - 1240
Cited by:  Papers (6)
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Conventionally, inductor current is sensed and quantized before it can be used by digitally controlled DC-DC converters. These are intuitively done by using two separated functional blocks-an analog current sensor and an ADC. A few research works have investigated other ways of obtaining the inductor current information in the digital domain. This paper proposes an on-chip digital inductor current... View full abstract»

• Resistive Computing: Memristors-Enabled Signal Multiplication

Publication Year: 2013, Page(s):1241 - 1249
Cited by:  Papers (27)
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Memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed out... View full abstract»

• Filtering of Markovian Jump Delay Systems Based on a New Performance Index

Publication Year: 2013, Page(s):1250 - 1263
Cited by:  Papers (120)
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This paper is concerned with the design of mode-dependent and mode-independent filters for continuous-time linear Markovian jump systems (MJSs) with time-varying delays. Different from the existing studies in the literature, the purpose of this paper is to solve the H∞, L2 - L∞ passive and dissipative filtering problems in a unified framework. This pu... View full abstract»

• A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator

Publication Year: 2013, Page(s):1264 - 1273
Cited by:  Papers (3)
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A 6-GHz phase-locked loop based spread-spectrum clock generator employing a self-oscillating technique is proposed. The clock generator adopts the property of the inherent oscillation of a charge-pump PLL while introducing no extra quantization noise. With the amplitude and frequency control, modulation frequency and frequency deviation can be tuned at 31.5 kHz and 5000 ppm, respectively. The meas... View full abstract»

• Delta-Sigma FDC Based Fractional-N PLLs

Publication Year: 2013, Page(s):1274 - 1285
Cited by:  Papers (11)  |  Patents (2)
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Fractional-N phase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (ΔΣ-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone ... View full abstract»

• Comparator Metastability in the Presence of Noise

Publication Year: 2013, Page(s):1286 - 1299
Cited by:  Papers (9)
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Metastability is the inability of a latched comparator to reach a decision in the available amount of time. Existing analyses of metastability disregard noise, treating it as a deterministic phenomenon that inevitably happens every-time the input voltage, vIdiff, falls in a certain interval around 0, and which is restricted to the aforementioned interval. Also, according to the conventi... View full abstract»

• Tunable Class AB CMOS Gm-C Filter Based on Quasi-Floating Gate Techniques

Publication Year: 2013, Page(s):1300 - 1309
Cited by:  Papers (13)
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A tunable CMOS Gm-C channel-select low-pass filter is presented. Class AB operation overcomes the dynamic range versus static power tradeoff of conventional channel-select filter topologies. Programmable transconductors are designed using quasi-floating gate transistors, which provide class AB operation without requiring extra supply voltage or power requirements and keeping accurately set quiesce... View full abstract»

• A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

Publication Year: 2013, Page(s):1310 - 1321
Cited by:  Papers (3)
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In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a ΔΣ ADC. The 0.13 μm CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The... View full abstract»

• Design of Low-Power Direct-Conversion RF Front-End With a Double Balanced Current-Driven Subharmonic Mixer in 0.13 $mu {rm m}$ CMOS

Publication Year: 2013, Page(s):1322 - 1330
Cited by:  Papers (13)
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A 402-MHz fully differential RF front-end was designed and implemented using 0.13 μm CMOS process. This design was targeted for low-power and low-cost direct conversion applications such as short-range radio in biomedical devices. This RF front-end consists of a differential CG-CS LNA with a positiveor negative-feedback technique and a frequency doubler subharmonic quadrature passive mixer.... View full abstract»

• CMOS Imager With Focal-Plane Analog Image Compression Combining DPCM and VQ

Publication Year: 2013, Page(s):1331 - 1344
Cited by:  Papers (17)
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CMOS imagers, in comparison to CCD image sensors, have the great advantage of allowing for the implementation of signal processing circuitry inside the pixel matrix. We can extract information of interest from an image prior to analog-to-digital conversion. In this work, we present a 32 × 32 imaging integrated circuit that captures and compresses gray scale images on the focal plane of the ... View full abstract»

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK