# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2013, Page(s):C1 - C4
| PDF (138 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2013, Page(s): C2
| PDF (134 KB)
• ### Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor

Publication Year: 2013, Page(s):257 - 267
Cited by:  Papers (19)  |  Patents (1)
| | PDF (2886 KB) | HTML

This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their ... View full abstract»

• ### A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

Publication Year: 2013, Page(s):268 - 278
Cited by:  Papers (17)
| | PDF (2832 KB) | HTML

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architec... View full abstract»

• ### An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

Publication Year: 2013, Page(s):279 - 289
Cited by:  Papers (15)
| | PDF (3307 KB) | HTML

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is ... View full abstract»

• ### NEMS-Based Functional Unit Power-Gating: Design, Analysis, and Optimization

Publication Year: 2013, Page(s):290 - 302
Cited by:  Papers (12)
| | PDF (1385 KB) | HTML

In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have ze... View full abstract»

• ### A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process

Publication Year: 2013, Page(s):303 - 313
Cited by:  Papers (4)
| | PDF (1984 KB) | HTML

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limi... View full abstract»

• ### Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

Publication Year: 2013, Page(s):314 - 326
Cited by:  Papers (12)
| | PDF (2251 KB) | HTML

This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for hyperbolic trajectory. We use most-significant-1 bit detection technique for micro-rotation sequence generation to reduce the number of iterations. By storing the sinh/cosh hyperbolic values at octant boundaries in a ROM, we can extend the range of convergence to the entire coordinate space. Based on this, we... View full abstract»

• ### A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $mu{rm m}$ CMOS

Publication Year: 2013, Page(s):327 - 340
Cited by:  Papers (15)
| | PDF (2827 KB) | HTML

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-... View full abstract»

• ### Stability and Stabilization for Markovian Jump Time-Delay Systems With Partially Unknown Transition Rates

Publication Year: 2013, Page(s):341 - 351
Cited by:  Papers (36)
| | PDF (3699 KB) | HTML

This paper focuses on the stability analysis and controller synthesis of continuous-time Markovian jump time-delay systems with incomplete transition rate descriptions. A general stability criterion is formulated first for state- and input-delay Markovian jump time-delay systems with fully known transition rates. On the basis of the proposed condition, an equivalent condition is given under the as... View full abstract»

• ### Finite-Time Distributed Tracking Control for Multi-Agent Systems With a Virtual Leader

Publication Year: 2013, Page(s):352 - 362
Cited by:  Papers (62)
| | PDF (3456 KB) | HTML

This paper aims at further investigating the finite-time distributed tracking control problems for multi-agent systems with a virtual leader under the conditions of fixed and switching topologies, respectively. Two continuous distributed tracking protocols are designed for tracking the virtual leader in finite time. Compared with the traditional distributed tracking protocols, the proposed distrib... View full abstract»

• ### Synchronization of Randomly Coupled Neural Networks With Markovian Jumping and Time-Delay

Publication Year: 2013, Page(s):363 - 376
Cited by:  Papers (72)
| | PDF (5568 KB) | HTML

This paper studies synchronization in an array of coupled neural networks with Markovian jumping and random coupling strength. The array of neural networks are coupled in a random fashion which is governed by Bernoulli random variable and each node has an interval time-varying delay. By designing a novel Lyapunov functional, using some inequalities and the properties of random variables, several d... View full abstract»

• ### Stability of Coupled Local Minimizers Within the Lagrange Programming Network Framework

Publication Year: 2013, Page(s):377 - 388
Cited by:  Papers (4)
| | PDF (2976 KB) | HTML

Coupled local minimizers (CLMs) turn out to be a potential global optimization strategy to explore a search space, avoid overfitting and produce good generalization. In this paper, convergence properties of CLMs based on an augmented Lagrangian function in the context of equality constrained minimization, are studied. We first consider the augmented Lagrangian by taking the objective of minimizing... View full abstract»

• ### Stabilization of Discrete-Time Systems With Multiple Actuator Delays and Saturations

Publication Year: 2013, Page(s):389 - 400
Cited by:  Papers (15)
| | PDF (3457 KB) | HTML

This paper studies the problems of global and semi-global stabilization of discrete-time linear systems with multiple input saturations and arbitrarily large bounded delays. By developing the methodology of truncated predictor feedback (TPF), state feedback control laws using only the current states of the systems are constructed to solve these problems. The feedback gains are dependent on the del... View full abstract»

• ### Robust Information Fusion Estimator for Multiple Delay-Tolerant Sensors With Different Failure Rates

Publication Year: 2013, Page(s):401 - 414
Cited by:  Papers (42)
| | PDF (4257 KB) | HTML

In this paper, the robust information fusion Kalman filtering problem is considered for multi-sensor systems with parameter uncertainties, randomly delayed measurements and sensor failures. The stochastic parameter perturbations are included in the state space models such that the proposed fusion estimator has robustness for the varying system parameters. For each observation subsystem, multiple b... View full abstract»

• ### Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters

Publication Year: 2013, Page(s):415 - 427
Cited by:  Papers (22)
| | PDF (2616 KB) | HTML

Burst-mode operation of power amplifiers (PAs) is a promising concept towards higher power efficiency in radio frequency (RF) transmitters. Such transmitters use pulse-width modulation (PWM) to create the driving signal for the PA, and a reconstruction filter after amplification to obtain the transmission signal. However, conventional digital pulse-width modulated signals contain a large amount of... View full abstract»

• ### A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications

Publication Year: 2013, Page(s):428 - 436
Cited by:  Papers (2)
| | PDF (2874 KB) | HTML

In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the pro... View full abstract»

• ### A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver

Publication Year: 2013, Page(s):437 - 447
Cited by:  Papers (7)
| | PDF (2232 KB) | HTML

A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-μm CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductor... View full abstract»

Publication Year: 2013, Page(s):448 - 456
Cited by:  Papers (11)
| | PDF (2064 KB) | HTML

A low-noise, high-gain, wide-linear-dynamic-range, wide-band receiver for a pulsed, direct, three-dimensional ranging LADAR system has been designed and implemented in a 0.13 μm CMOS technology. Specific design techniques, including gain control scheme to widen linear dynamic range, gain allocating between blocks and noise minimization to improve SNR, frequency response compensation to exte... View full abstract»

• ### A 0.18-/spl mu/m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

Publication Year: 2013, Page(s):457 - 468
Cited by:  Papers (15)
| | PDF (2701 KB) | HTML

A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM t... View full abstract»

• ### A 45-nm SOI CMOS Integrate-and-Dump Optical Sampling Receiver

Publication Year: 2013, Page(s):469 - 478
Cited by:  Papers (1)
| | PDF (2410 KB) | HTML

An integrate-and-dump receiver based on an active feedback integrator is demonstrated in a 45-nm SOI CMOS process. The integrate-and-dump receiver provides matched filtering for non-return-to-zero, return-to-zero, and pulse amplitude modulation digital modulation formats, resulting in high SINAD as well as inherent anti-aliasing/low-pass filtering for a 2 GS/s high linearity/high-dynamic-range opt... View full abstract»

• ### Analysis of Switching Circuits Through Incorporation of a Generalized Diode Reverse Recovery Model Into State Plane Analysis

Publication Year: 2013, Page(s):479 - 490
Cited by:  Papers (10)
| | PDF (2603 KB) | HTML

A new switching circuit analysis technique is proposed in which the reverse recovery and junction capacitance non-idealities of diode-based switches are incorporated into a state plane analysis of the circuit. Accurate state plane modeling of the reverse recovery process is based on the development of new generalizations of the classic charge control model. Using as an example a zero-voltage switc... View full abstract»

• ### Dimensionless Approach to Multi-Parametric Stability Analysis of Nonlinear Time-Periodic Systems: Theory and Its Applications to Switching Converters

Publication Year: 2013, Page(s):491 - 504
Cited by:  Papers (5)
| | PDF (3955 KB) | HTML

This paper proposes a dimensionless approach to analyze the multi-parametric stability behavior of switching converters, which can be characterized by a nonlinear time-periodic (NTP) system. The main objective is to analyze how multiple circuit parameters affect the stability patterns of the derived NTP system and to simplify the parametric complexity of such NTP system. In contrast to previous wo... View full abstract»

• ### Design of PWM Ramp Signal in Voltage-Mode CCM Random Switching Frequency Buck Converter for Conductive EMI Reduction

Publication Year: 2013, Page(s):505 - 515
Cited by:  Papers (10)
| | PDF (2694 KB) | HTML

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 &... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

Publication Year: 2013, Page(s): 516
| PDF (121 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK