IEEE Transactions on Circuits and Systems I: Regular Papers

This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it e... View full abstract»

All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the fr... View full abstract»

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that ... View full abstract»

This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufac... View full abstract»

Analog discrete-time finite-impulse-response (FIR) filters have been used as equalizers in digital communication receivers. For high speed applications, an FIR equalizer can be implemented using parallel sample-and-holds (S/Hs) and time-interleaved equalizer channels. Mismatches among the parallel S/Hs degrade the equalizer performance. This paper addresses mismatches of DC offsets, gain errors, s... View full abstract»

The object of this paper is to give a complete treatment of the realizability of positive-real biquadratic impedance functions by six-element series-parallel networks comprising resistors, capacitors, and inductors. This question was studied but not fully resolved in the classical electrical circuit literature. Renewed interest in this question arises in the synthesis of passive mechanical impedan... View full abstract»

Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation subcircuits. However, this results in fixed systems optimized for a given application at des... View full abstract»

Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current... View full abstract»

This paper presents an asynchronous digital technique for the realization of an integrator that takes as input the time-difference between two rising edges of digital signals and produces a corresponding time-difference output signal. The key element of this circuit is a time-memory cell called TLatch. This circuit has the ability to store the time-difference between two edges and allow its retrie... View full abstract»

Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. An option to protect memories against MCUs is to use advanced ECCs that can correct more than one error per word. In this area, the use of one step majority logic decodable codes has recently been proposed fo... View full abstract»

This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for seque... View full abstract»

This paper presents a circuit-theoretic foundation of the “memristor,” and clarifies why it is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memistor.” Here we show that while the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory, the memistor is an ad hoc 3-terminal gadget devised for one specific application, a... View full abstract»

The analysis of complicated circuits containing nonlinear electrical elements is commonly performed via numerical algorithms of simulation programs. However, an analytical solution can be preferable to the numerical approach, particularly for the needs of basic research. This paper introduces a methodology of the analytical solution of voltage/current response of the memristor to its excitation fr... View full abstract»

This paper proposes a novel constructive training algorithm for cascade neural networks. By reformulating the cascade neural network as a linear-in-the-parameters model, we use the orthogonal least squares (OLS) method to derive a novel objective function for training new hidden units. With this objective function, the sum of squared errors (SSE) of the network can be maximally reduced after each ... View full abstract»

A fast simulation method for time-derivative cellular neural networks (TDCNN) is proposed. Using forward Euler approximation (FEA) for the derivative of the cell state and the backward Euler approximation (BEA) for the derivatives of the neighboring cell states enables the recursive computation of the cell state and provides a speed advantage of orders of magnitude. The state equations are then pa... View full abstract»

This paper studies the leader-following finite-time consensus problem for the second-order multi-agent networks with fixed and switched topologies. Based on the graph theory, matrix theory, homogeneity with dilation and LaSalle's invariance principle, finite-time consensus protocols are designed by the pinning control technique without assuming that the interaction graph is connected or the leader... View full abstract»

In this paper, we address the synchronization problem of coupled partial differential systems (PDSs). First, the asymptotical synchronization and theH∞synchronization of N-coupled PDSs with space-independent coefficients are considered without or with spatio-temporal disturbance, respectively. The sufficient conditions to guarantee the asymptotical synchronization and theH... View full abstract»

For descriptor multi-agent systems with fixed topology and agents described by general descriptor linear time-invariant systems, necessary and sufficient conditions of consensusability with respect to a set of admissible consensus protocols are proposed using the tools of algebra, graph and descriptor linear system theory. The consensusability conditions depend on both the structure properties of ... View full abstract»

A novel electrical circuit spiking neuron model that has a piece-wise-constant vector field with a state-dependent reset is presented. It is shown that the model exhibits six kinds of border-collision bifurcations, where their bifurcation sets are derived and are summarized into two parameter diagrams. Then, using the diagrams, systematic synthesis procedures of the presented model so that it can ... View full abstract»

This paper presents a systematic framework to analyze the global pinning-controllability of general complex networks with or without time-delay based on the properties of M-matrices and directed spanning trees. Some stability criteria are established to guarantee that a network can be globally asymptotically pinned to a homogenous state. By partitioning the interaction diagraph into a minimum numb... View full abstract»

This paper considers chaos synchronization and chaos-based secure communication problems based on high-gain sliding mode unknown input observers when the observer matching condition is not satisfied to the drive signal. An auxiliary drive signal vector which satisfies the observer matching condition is introduced and an adaptive and robust observer is developed by using the auxiliary drive signal ... View full abstract»

A deep theoretical discussion proves that in Joglekar's and Biolek's models the memductance-flux relation of a memristor driven by a sign-varying voltage source may only exhibit single-valuedness and multi-valuedness respectively. This manuscript derives a novel boundary condition-based Model for memristor nanostructures. Unlike previous models, the proposed one allows for closed-form solutions. M... View full abstract»

This study proposes an autonomous distributed control method for single link failure based on loops in a network. This method focuses on the concept of tie-sets defined by graph theory in order to divide a network into a string of logical loops. A tie-set denotes a set of links that constitutes a loop. Based on theoretical rationale of graph theory, a string of tie-sets that cover all the nodes an... View full abstract»