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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 11 • Date Nov. 2012

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Displaying Results 1 - 25 of 34
  • Table of Contents

    Publication Year: 2012 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2012 , Page(s): C2
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  • An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique

    Publication Year: 2012 , Page(s): 2481 - 2494
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2573 KB) |  | HTML iconHTML  

    This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented. View full abstract»

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  • Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

    Publication Year: 2012 , Page(s): 2495 - 2506
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3307 KB) |  | HTML iconHTML  

    All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL. View full abstract»

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  • A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

    Publication Year: 2012 , Page(s): 2507 - 2517
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2482 KB) |  | HTML iconHTML  

    A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 μm CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply. View full abstract»

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  • A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation

    Publication Year: 2012 , Page(s): 2518 - 2528
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3796 KB) |  | HTML iconHTML  

    This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate. View full abstract»

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  • Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers

    Publication Year: 2012 , Page(s): 2529 - 2542
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2111 KB) |  | HTML iconHTML  

    Analog discrete-time finite-impulse-response (FIR) filters have been used as equalizers in digital communication receivers. For high speed applications, an FIR equalizer can be implemented using parallel sample-and-holds (S/Hs) and time-interleaved equalizer channels. Mismatches among the parallel S/Hs degrade the equalizer performance. This paper addresses mismatches of DC offsets, gain errors, sample-time errors, and bandwidths in the S/Hs. It is shown that having a different set of adapted coefficients in each equalizer channel can reduce the effects of mismatches. Simulation results are presented for different communication channels. View full abstract»

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  • Series-Parallel Six-Element Synthesis of Biquadratic Impedances

    Publication Year: 2012 , Page(s): 2543 - 2554
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2113 KB) |  | HTML iconHTML  

    The object of this paper is to give a complete treatment of the realizability of positive-real biquadratic impedance functions by six-element series-parallel networks comprising resistors, capacitors, and inductors. This question was studied but not fully resolved in the classical electrical circuit literature. Renewed interest in this question arises in the synthesis of passive mechanical impedances. Recent work by the authors has introduced the concept of a regular positive-real functions. It was shown that five-element networks are capable of realizing all regular and some (but not all) nonregular biquadratic positive-real functions. Accordingly, the focus of this paper is on the realizability of nonregular biquadratics. It will be shown that the only six-element series-parallel networks which are capable of realizing nonregular biquadratic impedances are those with three reactive elements or four reactive elements. We identify a set of networks that can realize all the nonregular biquadratic functions for each of the two cases. The realizability conditions for the networks are expressed in terms of a canonical form for biquadratics. The nonregular realizable region for each of the networks is explicitly characterized. View full abstract»

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  • A Flexible Low Power DSP With a Programmable Truncated Multiplier

    Publication Year: 2012 , Page(s): 2555 - 2568
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2756 KB) |  | HTML iconHTML  

    Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation subcircuits. However, this results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction tradeoff against signal degradation which can be modified at run time. Such an architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation is also shown to be effective when deploying truncated multipliers in a system. View full abstract»

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  • A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation

    Publication Year: 2012 , Page(s): 2569 - 2577
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1453 KB) |  | HTML iconHTML  

    Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of ~ 4 μW with 6 MHz at 0.5 V, which is 30% better than the counterpart design. View full abstract»

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  • A Digital Implementation of a Dual-Path Time-to-Time Integrator

    Publication Year: 2012 , Page(s): 2578 - 2591
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3005 KB) |  | HTML iconHTML  

    This paper presents an asynchronous digital technique for the realization of an integrator that takes as input the time-difference between two rising edges of digital signals and produces a corresponding time-difference output signal. The key element of this circuit is a time-memory cell called TLatch. This circuit has the ability to store the time-difference between two edges and allow its retrieval at a later time. By using two TLatches in parallel, a dual-path high-throughput integrator is proposed. Internal mismatches in delays can be removed using a simple calibration algorithm that aligns the frequency of two internal oscillators, thereby eliminating the need for trimming or any reference element. The proposed architecture is fabricated in 1.2 V 0.13-μm IBM CMOS technology and the experimental results confirm the integration operation. View full abstract»

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  • Multiple Cell Upset Correction in Memories Using Difference Set Codes

    Publication Year: 2012 , Page(s): 2592 - 2599
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB) |  | HTML iconHTML  

    Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. An option to protect memories against MCUs is to use advanced ECCs that can correct more than one error per word. In this area, the use of one step majority logic decodable codes has recently been proposed for memory applications. Difference Set (DS) codes are one example of these codes. In this paper, a scheme is presented to protect a memory from MCUs using Difference Set codes. The proposed scheme exploits the localization of the errors in an MCU, as well as the properties of DS codes, to provide enhanced error correction capabilities. The properties of the DS codes are also used to reduce the decoding time. The scheme has been implemented in HDL, and circuit area and speed estimates are provided. View full abstract»

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  • A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link

    Publication Year: 2012 , Page(s): 2600 - 2610
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2319 KB) |  | HTML iconHTML  

    This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively. View full abstract»

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  • Why Are Memristor and Memistor Different Devices?

    Publication Year: 2012 , Page(s): 2611 - 2618
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2132 KB) |  | HTML iconHTML  

    This paper presents a circuit-theoretic foundation of the “memristor,” and clarifies why it is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memistor.” Here we show that while the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory, the memistor is an ad hoc 3-terminal gadget devised for one specific application, and does not qualify as a 3-terminal circuit element because it is impossible to predict its behavior when connected with other circuit elements. View full abstract»

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  • Analytical Solution of Circuits Employing Voltage- and Current-Excited Memristors

    Publication Year: 2012 , Page(s): 2619 - 2628
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2153 KB) |  | HTML iconHTML  

    The analysis of complicated circuits containing nonlinear electrical elements is commonly performed via numerical algorithms of simulation programs. However, an analytical solution can be preferable to the numerical approach, particularly for the needs of basic research. This paper introduces a methodology of the analytical solution of voltage/current response of the memristor to its excitation from ideal current/voltage source, with the memristor being characterized by the memristance-charge or memductance-flux relationships. The procedure is explained on examples of a TiO2 memristor with linear dopant drift and of a hydraulic memristor. View full abstract»

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  • Orthogonal Least Squares Algorithm for Training Cascade Neural Networks

    Publication Year: 2012 , Page(s): 2629 - 2637
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2119 KB) |  | HTML iconHTML  

    This paper proposes a novel constructive training algorithm for cascade neural networks. By reformulating the cascade neural network as a linear-in-the-parameters model, we use the orthogonal least squares (OLS) method to derive a novel objective function for training new hidden units. With this objective function, the sum of squared errors (SSE) of the network can be maximally reduced after each new hidden unit is added, thus leading to a network with less hidden units and better generalization performance. Furthermore, the proposed algorithm considers both the input weights training and output weights training in an integrated framework, which greatly simplifies the training of output weights. The effectiveness of the proposed algorithm is demonstrated by simulation results. View full abstract»

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  • Efficient Simulation of Time-Derivative Cellular Neural Networks

    Publication Year: 2012 , Page(s): 2638 - 2645
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2869 KB) |  | HTML iconHTML  

    A fast simulation method for time-derivative cellular neural networks (TDCNN) is proposed. Using forward Euler approximation (FEA) for the derivative of the cell state and the backward Euler approximation (BEA) for the derivatives of the neighboring cell states enables the recursive computation of the cell state and provides a speed advantage of orders of magnitude. The state equations are then packed into a vector-matrix form which enables the previously empirically given time constraint to be expressed as a matrix condition. It is shown that using both FEA and BEA leads to a second-order difference equation whose corresponding second-order differential equation is derived and shown to yield the same simulation results. View full abstract»

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  • Finite-Time Consensus for Leader-Following Second-Order Multi-Agent Networks

    Publication Year: 2012 , Page(s): 2646 - 2654
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2547 KB) |  | HTML iconHTML  

    This paper studies the leader-following finite-time consensus problem for the second-order multi-agent networks with fixed and switched topologies. Based on the graph theory, matrix theory, homogeneity with dilation and LaSalle's invariance principle, finite-time consensus protocols are designed by the pinning control technique without assuming that the interaction graph is connected or the leader is globally reachable. Moreover, the control protocol of each agent using local information is presented, and some examples and simulation results are given to illustrate the effectiveness of the obtained theoretical results. View full abstract»

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  • Synchronization of Partial Differential Systems via Diffusion Coupling

    Publication Year: 2012 , Page(s): 2655 - 2668
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5031 KB) |  | HTML iconHTML  

    In this paper, we address the synchronization problem of coupled partial differential systems (PDSs). First, the asymptotical synchronization and the H synchronization of N-coupled PDSs with space-independent coefficients are considered without or with spatio-temporal disturbance, respectively. The sufficient conditions to guarantee the asymptotical synchronization and the H synchronization are derived. The effect of the spatial domain on the synchronization of the coupled PDSs is also presented. Then the problem of asymptotical synchronization of N-coupled PDSs with space-dependent coefficients is dealt with and the sufficient condition to guarantee the asymptotical synchronization is obtained by using the Lyapunov-Krasovskii method. The condition of the H synchronization for N-coupled PDSs with space-dependent coefficients is also presented. Both conditions are given by integral inequalities, which are difficult to be verified. In order to avoid solving these integral inequalities, we adopt the semi-discrete difference method to turn the PDSs into an equivalent spatial space state system, then the sufficient condition of the H synchronization for N-coupled PDSs is given by an LMI, which is easier to be verified. Further, the relationship between the sufficient conditions for the H synchronization, obtained by the Lyapunov-Krasovskii method and semi-discrete difference method respectively, is investigated. Finally, two examples of coupled PDSs are given to illustrate the correctness of our results obtained in this paper. View full abstract»

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  • Necessary and Sufficient Consensus Conditions of Descriptor Multi-agent Systems

    Publication Year: 2012 , Page(s): 2669 - 2677
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2326 KB) |  | HTML iconHTML  

    For descriptor multi-agent systems with fixed topology and agents described by general descriptor linear time-invariant systems, necessary and sufficient conditions of consensusability with respect to a set of admissible consensus protocols are proposed using the tools of algebra, graph and descriptor linear system theory. The consensusability conditions depend on both the structure properties of each agent's dynamics and the topology within the descriptor multi-agent systems. Designing an output feedback control law can guarantee that the studied descriptor multi-agent system is consensusable with respect to a given admissible set. A provided example indicates the applicability of the proposed approach. View full abstract»

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  • A Novel PWC Spiking Neuron Model: Neuron-Like Bifurcation Scenarios and Responses

    Publication Year: 2012 , Page(s): 2678 - 2691
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3782 KB) |  | HTML iconHTML  

    A novel electrical circuit spiking neuron model that has a piece-wise-constant vector field with a state-dependent reset is presented. It is shown that the model exhibits six kinds of border-collision bifurcations, where their bifurcation sets are derived and are summarized into two parameter diagrams. Then, using the diagrams, systematic synthesis procedures of the presented model so that it can reproduce four kinds of bifurcation scenarios that are typically observed in standard neuron models are presented. It is shown that the model can reproduce the bifurcation scenarios as well as corresponding nonlinear response characteristics observed in model and biological neurons. Occurrences of typical neuron-like bifurcations are confirmed by experimental measurements. View full abstract»

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  • Pinning-Controllability Analysis of Complex Networks: An M-Matrix Approach

    Publication Year: 2012 , Page(s): 2692 - 2701
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2390 KB) |  | HTML iconHTML  

    This paper presents a systematic framework to analyze the global pinning-controllability of general complex networks with or without time-delay based on the properties of M-matrices and directed spanning trees. Some stability criteria are established to guarantee that a network can be globally asymptotically pinned to a homogenous state. By partitioning the interaction diagraph into a minimum number of components, a selective pinning scheme for a complex network with arbitrary topology is proposed to determine the number and the locations of the pinned nodes. In particular, this paper deeply investigates the roles of network nodes in the pinning control, including what kind of nodes should be pinned and what kind of nodes may be left unpinned. Numerical simulations are given to verify the theoretical analysis. View full abstract»

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  • The Combination of High-Gain Sliding Mode Observers Used as Receivers in Secure Communication

    Publication Year: 2012 , Page(s): 2702 - 2712
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2611 KB) |  | HTML iconHTML  

    This paper considers chaos synchronization and chaos-based secure communication problems based on high-gain sliding mode unknown input observers when the observer matching condition is not satisfied to the drive signal. An auxiliary drive signal vector which satisfies the observer matching condition is introduced and an adaptive and robust observer is developed by using the auxiliary drive signal directly to not only estimate the states but also adjust adaptively the unknown parameters and the Lipschitz constants of the nonlinear terms. A high-gain sliding mode observer is considered to exactly estimate both the auxiliary drive signals and their derivatives in a finite time only based on the original drive signal. The combination of the adaptive and robust observer and the high-gain sliding mode observer becomes the receiver in chaos-based secure communication discussion. A kind of information signal recovering method is developed based on both the state synchronization and exact estimates of the derivatives of the auxiliary drive signals. Finally, a numerical simulation example is given to illustrate the effectiveness of the proposed methods. View full abstract»

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  • A Boundary Condition-Based Approach to the Modeling of Memristor Nanostructures

    Publication Year: 2012 , Page(s): 2713 - 2726
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3264 KB) |  | HTML iconHTML  

    A deep theoretical discussion proves that in Joglekar's and Biolek's models the memductance-flux relation of a memristor driven by a sign-varying voltage source may only exhibit single-valuedness and multi-valuedness respectively. This manuscript derives a novel boundary condition-based Model for memristor nanostructures. Unlike previous models, the proposed one allows for closed-form solutions. More importantly, subject to the nonlinear behavior under exam, this model enables a suitable tuning of boundary conditions, which may result in the detection of both single-valued and multi-valued memductance-flux relations under certain sign-varying inputs of interest. The large class of modeled dynamics include all behaviors reported in the legendary paper revealing the existence of memory-resistance at the nano scale. View full abstract»

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  • An Autonomous Distributed Control Method for Link Failure Based on Tie-Set Graph Theory

    Publication Year: 2012 , Page(s): 2727 - 2737
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2065 KB) |  | HTML iconHTML  

    This study proposes an autonomous distributed control method for single link failure based on loops in a network. This method focuses on the concept of tie-sets defined by graph theory in order to divide a network into a string of logical loops. A tie-set denotes a set of links that constitutes a loop. Based on theoretical rationale of graph theory, a string of tie-sets that cover all the nodes and links can be created by using a tree, even in an intricately-intertwined mesh network. If tie-sets are used as local management units, high-speed and stable fail-over can be realized by taking full advantage of ring-based restoration. This paper first introduces the notion of tie-sets, and then describes the distributed algorithms for link failure. Experiments are conducted against Rapid Spanning Tree Protocol (RSTP), which is generally used for fault recovery in mesh topological networks. Experimental results comparing the proposed method with RSTP suggest that our method alleviates the adverse effects of link failure with a modest increase in state information of a node. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras