IEEE Transactions on Circuits and Systems I: Regular Papers

Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2012, Page(s):C1 - C4
| PDF (47 KB)
• IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2012, Page(s): C2
| PDF (132 KB)
• Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011)

Publication Year: 2012, Page(s):1601 - 1603
| PDF (606 KB) | HTML
• A 12.5-bit 4 MHz 13.8 mW MASH $Delta Sigma$ Modulator With Multirated VCO-Based ADC

Publication Year: 2012, Page(s):1604 - 1613
Cited by:  Papers (11)
| | PDF (1759 KB) | HTML

A novel MASH delta-sigma (ΔΣ) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second... View full abstract»

• A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $Delta Sigma$ Modulator Dissipating 16 mW Power

Publication Year: 2012, Page(s):1614 - 1625
Cited by:  Papers (18)  |  Patents (1)
| | PDF (1587 KB) | HTML

This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of... View full abstract»

• Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS

Publication Year: 2012, Page(s):1626 - 1634
Cited by:  Papers (14)
| | PDF (1854 KB) | HTML

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design tr... View full abstract»

• Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM

Publication Year: 2012, Page(s):1635 - 1643
Cited by:  Papers (3)
| | PDF (2267 KB) | HTML

A statistical threshold voltage VTH shift variation of the pass gate (PG) transistor in local electron injected asymmetric PG transistor 6T-SRAM is investigated. Measurements show that the positive correlation between the PG transistor VTH shift (VTHPG shift) and its original VTH of the PG transistor (VTHPG) ... View full abstract»

• An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

Publication Year: 2012, Page(s):1644 - 1655
Cited by:  Papers (2)
| | PDF (3263 KB) | HTML

This work presents the first case of using the pseudoexhaustive testing (PET) for high-speed high-order (>;32 -bit) adders. It is shown that all single stack-at faults are detected by a pseudoexhaustive test set of 54 K patterns, compared to 264×2 patterns in the past. Also, all transition faults are detected by a pseudoexhaustive test set of 13 M patterns, compared to 26... View full abstract»

• A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

Publication Year: 2012, Page(s):1656 - 1666
Cited by:  Papers (8)
| | PDF (4355 KB) | HTML

We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a v... View full abstract»

Publication Year: 2012, Page(s):1667 - 1679
Cited by:  Papers (5)
| | PDF (1181 KB) | HTML

A key role in determining the overall performance of a communication link is played by the linearity of the analog sections of the transmitter and the receiver. Nonlinearity in the receiver can impact performance in several ways, including degradation in sensitivity, reduction in gain, and the appearance of spurious energy within the frequency band of interest from out-of-band sources. An overview... View full abstract»

• Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon

Publication Year: 2012, Page(s):1680 - 1693
Cited by:  Papers (17)  |  Patents (1)
| | PDF (2797 KB) | HTML

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of diffe... View full abstract»

• A 0.6-V Quadrature VCO With Enhanced Swing and Optimized Capacitive Coupling for Phase Noise Reduction

Publication Year: 2012, Page(s):1694 - 1705
Cited by:  Papers (22)
| | PDF (2226 KB) | HTML

This paper presents a 0.6-V quadrature voltage-controlled oscillator (QVCO) with enhanced swing for low power supply applications. The QVCO comprises a novel capacitive coupling technique that is employed not only for quadrature signal coupling, but also for phase noise reduction. As a result, the proposed QVCO can even achieve 4.6 dB lower phase noise than its single-phase counterpart at 3-MHz of... View full abstract»

• A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Publication Year: 2012, Page(s):1706 - 1719
Cited by:  Papers (16)  |  Patents (1)
| | PDF (3435 KB) | HTML

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed ... View full abstract»

• A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration

Publication Year: 2012, Page(s):1720 - 1732
Cited by:  Papers (24)
| | PDF (3971 KB) | HTML

A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By impl... View full abstract»

• The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Publication Year: 2012, Page(s):1733 - 1742
Cited by:  Papers (7)
| | PDF (1852 KB) | HTML

An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. Wh... View full abstract»

• A Dual-Band 2.45/6 GHz CMOS LNA Utilizing a Dual-Resonant Transformer-Based Matching Network

Publication Year: 2012, Page(s):1743 - 1751
Cited by:  Papers (26)
| | PDF (1661 KB) | HTML

This paper analyzes and presents design equations for a new transformer-based matching network capable of simultaneously matching two different frequencies. This network is then used to realize a dual-band low-noise amplifier that is fabricated in a 0.13 μm CMOS process and is capable of operating at 2.45 GHz and 6 GHz. The measured S21 and noise figure for 2.45 GHz (6 GHz) is 9.... View full abstract»

• A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

Publication Year: 2012, Page(s):1752 - 1765
Cited by:  Papers (26)
| | PDF (4196 KB) | HTML

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly un... View full abstract»

• Bi-Minimax Design of Even-Order Variable Fractional-Delay FIR Digital Filters

Publication Year: 2012, Page(s):1766 - 1774
Cited by:  Papers (19)
| | PDF (2437 KB) | HTML

This paper proposes a new minimax method for designing even-order finite-impulse-response (FIR) variable fractional-delay (VFD) digital filters with both the peak errors (maximum absolute errors) of variable frequency response (VFR) and VFD response being minimized. We call such a new minimax design the bi-minimax design, which minimizes a mixed error function that contains both the VFR peak error... View full abstract»

• A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

Publication Year: 2012, Page(s):1775 - 1785
Cited by:  Papers (20)
| | PDF (1895 KB) | HTML

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational para... View full abstract»

• Stabilization and Synchronization of Complex Dynamical Networks With Different Dynamics of Nodes Via Decentralized Controllers

Publication Year: 2012, Page(s):1786 - 1795
Cited by:  Papers (29)
| | PDF (2640 KB) | HTML

This paper investigates the stabilization and synchronization of complex dynamical networks with different dynamics of nodes by using decentralized linear control and linear matrix inequality. We propose a dynamical network model with similar nodes that the dimensions of node dynamics are different. For this kind of network model, decentralized linear controllers are designed for the stabilization... View full abstract»

• Characterization of Analog Circuits Using Transfer Function Trajectories

Publication Year: 2012, Page(s):1796 - 1804
Cited by:  Papers (13)
| | PDF (2653 KB) | HTML

A methodology is presented to characterize and model strongly nonlinear behavior of analog circuits with a compact set of nonlinear differential equations. While simulating a circuit in the time domain, the nodal matrix is extracted at each time step, similar to trajectory piecewise sampling (TPW). The circuit snapshots projected on a frequency-state space domain to facilitate the regression probl... View full abstract»

• A Primary Side Control Method for Wireless Energy Transmission System

Publication Year: 2012, Page(s):1805 - 1814
Cited by:  Papers (11)  |  Patents (1)
| | PDF (1806 KB) | HTML

This paper presents a primary side control method for a low power wireless energy transmission system (WETS), with no physical wire connection required between the primary and secondary-side circuits. The primary side control method implemented in the WETS does not require extra space in the secondary side to regulate transmission energy. A charging protection was embedded within the secondary sid... View full abstract»

• Robust Near-Threshold Design With Fine-Grained Performance Tunability

Publication Year: 2012, Page(s):1815 - 1825
Cited by:  Papers (7)
| | PDF (2120 KB) | HTML

Lowering supply voltage is still the most effective technique to reduce dynamic power, and Vdd is being pushed toward the threshold voltage for ultra-low power applications. However, near-threshold circuit leakage power is comparable to the switching power and performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance ... View full abstract»

• IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

Publication Year: 2012, Page(s): 1826
| PDF (117 KB)
• 2012 IEEE membership form

Publication Year: 2012, Page(s):1827 - 1828
| PDF (1368 KB)

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK