# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2012, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2012, Page(s): C2
| PDF (39 KB)
• ### Guest Editorial Special Issue on ISCAS 2011

Publication Year: 2012, Page(s): 905
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• ### An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

Publication Year: 2012, Page(s):906 - 914
Cited by:  Papers (8)
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This paper presents a parallel sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With this technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence th... View full abstract»

• ### A 1-V 15-Bit Audio$\Delta \Sigma$-ADC in 0.18$\mu$m CMOS

Publication Year: 2012, Page(s):915 - 925
Cited by:  Papers (11)  |  Patents (1)
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In this paper a 1-V supply, 15-bit ΔΣ ADC design for audio applications is presented. The second order CIFB ΔΣ modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate ref... View full abstract»

• ### Quantization Noise Suppression in Fractional-$N$PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

Publication Year: 2012, Page(s):926 - 937
Cited by:  Papers (12)  |  Patents (1)
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A novel programmable frequency divider for quantization noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed phase switching multi-modulus frequency divider (PS-MMFD) utilizes a novel glitch-free phase switching (PS) divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and its QN induced by ΔΣ modulation is thus suppressed by ... View full abstract»

• ### An Analysis of$1/f$Noise to Phase Noise Conversion in CMOS Harmonic Oscillators

Publication Year: 2012, Page(s):938 - 945
Cited by:  Papers (21)  |  Patents (1)
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We present a study of tail-bias-current 1/fnoise upconversion into 1/f3phase noise for both CMOS Colpitts and differential-pairLCoscillators. We focus on the incremental Groszkowski effect, i.e., the modulation of the shift in oscillation frequency induced by the higher current harmonics flowing into theLCtank of a harmonic oscillator induced by bias instabil... View full abstract»

• ### A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA

Publication Year: 2012, Page(s):946 - 957
Cited by:  Papers (23)
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Most of the traditional RF circuits are static or minimally tunable using some digital controllability. For example, high power, low power and shut down modes are available in some commercially available transceivers. If available, the tuning knobs affect different specifications in an interdependent manner, resulting in changing several specifications when only one needs to be tuned. This is not ... View full abstract»

• ### Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Publication Year: 2012, Page(s):958 - 968
Cited by:  Papers (23)
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Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital ... View full abstract»

• ### Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator

Publication Year: 2012, Page(s):969 - 978
Cited by:  Papers (1)  |  Patents (1)
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This paper proposes the use of a digital ΣΔ modulator with pseudorandom variation of coefficients. The method improves PLL-based Fractional Frequency Synthesizer's performance while using a low order digital ΣΔ modulator. The time variant coefficients, in a low order digital ΣΔ modulator, significantly enlarge the pseudorandom output pattern period thus avoiding critical spur tones in the fraction... View full abstract»

• ### An Empirical Phase-Noise Model for MEMS Oscillators Operating in Nonlinear Regime

Publication Year: 2012, Page(s):979 - 988
Cited by:  Papers (18)
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Nonlinearity of a silicon resonator can lead to improved phase-noise performance in an oscillator when the phase shift of the sustaining amplifier forces the operating point to a steeper phase-frequency slope. As a result, phase modulation on the oscillator frequency is minimized because the resonator behaves as a high-order phase filter. The effect of the increased filtering translates into phase... View full abstract»

• ### Improved Methods for the Design of Variable Fractional-Delay IIR Digital Filters

Publication Year: 2012, Page(s):989 - 1000
Cited by:  Papers (7)
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In this paper, both methods of magnitude-oriented design and delay-oriented design for variable fractional-delay (VFD) infinite impulse response (IIR) filters are proposed. In the former, the objective error function is formed by including root-mean-square error function of variable frequency response and the stability error constrained function, such that the designed filters are stable. As for t... View full abstract»

• ### Rakeness in the Design of Analog-to-Information Conversion of Sparse and Localized Signals

Publication Year: 2012, Page(s):1001 - 1014
Cited by:  Papers (49)
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Design of random modulation preintegration systems based on the restricted-isometry property may be suboptimal when the energy of the signals to be acquired is not evenly distributed, i.e., when they are both sparse and localized. To counter this, we introduce an additional design criterion, that we call rakeness, accounting for the amount of energy that the measurements capture from the signal to... View full abstract»

• ### Design and Implementation of Grid Multiwing Hyperchaotic Lorenz System Family via Switching Control and Constructing Super-Heteroclinic Loops

Publication Year: 2012, Page(s):1015 - 1028
Cited by:  Papers (52)
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This paper initiates a systematic methodology for generating various grid multiwing hyperchaotic attractors by switching control and constructing super-heteroclinic loops from the piecewise linear hyperchaotic Lorenz system family. By linearizing the three-dimensional generalized Lorenz system family at their two symmetric equilibria and then introducing the state feedback, two fundamental four-di... View full abstract»

• ### Synchronization of Networks of Non-Identical Chua's Circuits: Analysis and Experiments

Publication Year: 2012, Page(s):1029 - 1041
Cited by:  Papers (20)
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This paper is concerned with the theoretical and experimental analysis of synchronization and pinning control of networks of non-identical Chua's circuits. The design and implementation is presented of an appropriate setup to carry out experiments on networks of these nonlinear circuits with easily reconfigurable parameter values. Then, the theoretical expectations are validated of the so-called E... View full abstract»

• ### Synchronization in Several Types of Coupled Polygonal Oscillatory Networks

Publication Year: 2012, Page(s):1042 - 1050
Cited by:  Papers (8)
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In this study, synchronization phenomena observed in several types of coupled polygonal oscillatory networks by sharing branches are investigated by both computer simulations and circuit experiments. We focus on the power consumption of coupling resistors of the whole system. By using theoretical analysis, we confirm that the phase differences of the coupled oscillators are solved by finding the m... View full abstract»

• ### Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array

Publication Year: 2012, Page(s):1051 - 1060
Cited by:  Papers (12)
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Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory ... View full abstract»

• ### RF Analog Beamforming Fan Filters Using CMOS All-Pass Time Delay Approximations

Publication Year: 2012, Page(s):1061 - 1073
Cited by:  Papers (20)
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A continuous-time (CT) radio frequency (RF) antenna array beamformer and analog circuit based on a discrete-space-continuous-time (DSCT) 2-D fan-filter having transfer function HF,A(zx,sct) is derived. The proposed transfer function is based on a 2-D FIR discrete domain fan filter. The discrete domain prototype is converted to the proposed mixed-domain DSCT analog ... View full abstract»

• ### Frequency Domain Analysis of Superregenerative Receivers in the Linear and the Logarithmic Modes

Publication Year: 2012, Page(s):1074 - 1084
Cited by:  Papers (6)
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Despite their simplicity, analysis and design of superregenerative oscillators is often still based on approximations which provide limited insight into its behavior. In this paper we investigate the superregenerative oscillator in the linear and logarithmic operation modes without any approximations. A frequency-domain formulation allows us to efficiently compute the relevant waveforms both in th... View full abstract»

• ### An Image Frequency Rejection Filter for SAW-Less GPS Receivers

Publication Year: 2012, Page(s):1085 - 1092
Cited by:  Papers (2)
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We have developed an on-chip RF filter in 130 nm BiCMOS for SAW-less GPS receivers. The filter is implemented as a cascode amplifier stage with reactive resonant tanks. The filter employs two Q-enhanced LC tanks to create a transfer function with steep roll-off characteristic and narrow passband. The image rejection filter achieves a 3 dB bandwidth of less than 12 MHz at the GPS L<sub>1</... View full abstract»

• ### An Algorithm to Compensate the Effects of Spurious PLL Tones in Spectrum Sensing Architectures

Publication Year: 2012, Page(s):1093 - 1106
Cited by:  Papers (2)  |  Patents (1)
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In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used as a sampling clock to an analog-to-digital converter (ADC), it creates spurious sidebands in the sampled data as well. In spectrum sensing applications, the presence of spurious sidebands can lead to false detection of signals in otherwise empty channels.... View full abstract»

• ### VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

Publication Year: 2012, Page(s):1107 - 1118
Cited by:  Papers (37)  |  Patents (2)
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Spectrally efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the key research challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. Focusing on transmitters, this paper explains the SEFDM concept and examines the complexity of published modulatio... View full abstract»

• ### An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC

Publication Year: 2012, Page(s):1119 - 1131
Cited by:  Papers (45)
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This paper presents an output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current... View full abstract»

• ### Analysis and Design of a High-Voltage-Gain Hybrid Switched-Capacitor Buck Converter

Publication Year: 2012, Page(s):1132 - 1141
Cited by:  Papers (23)
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This paper presents an analysis on the effect of having different number of capacitors <i>n</i> in the first-stage switched-capacitor circuit of an improved hybrid switched-capacitor buck converter for high-voltage-gain conversion. Various aspects of the topology, operation, and efficiency are investigated. It is shown both analytically and experimentally that a higher <i>n</i... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

Publication Year: 2012, Page(s): 1142
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK