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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 4 • Date April 2011

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Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

    Publication Year: 2011 , Page(s): 645 - 653
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (547 KB) |  | HTML iconHTML  

    Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. View full abstract»

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  • On the Noise Optimization of CMOS Common-Source Low-Noise Amplifiers

    Publication Year: 2011 , Page(s): 654 - 667
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB) |  | HTML iconHTML  

    In this paper, we propose a general noise optimization technique for the CMOS common-source low-noise amplifiers. By directly employing the short-channel MOSFET - characteristic and van der Ziel's noise model, we derive design equations for the selection of the circuit design parameters, such as transistor sizes, passive component values, and bias voltages, which are subject to various gain and current consumption constraints. We also include several side effects, including the finite quality factor and the back-gate transconductance into the optimization process, and analyze their impact on the optimization results. Design examples that are based on a virtual but realistic process are given to verify our analysis and to give design intuition. View full abstract»

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  • Analysis of \hbox {IM}_{\rm 3} Asymmetry in MOSFET Small-Signal Amplifiers

    Publication Year: 2011 , Page(s): 668 - 676
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2348 KB) |  | HTML iconHTML  

    This paper describes and analyzes asymmetry issues for weakly nonlinear MOSFET Common-Gate (CG) and Common-Source (CS) architectures. Using a Volterra series analysis, the cause of asymmetry in CG and CS amplifiers is explained. The asymmetry between high-side and low-side products in the CG amplifier exhibits a larger amplitude difference at low-frequency offset than at high frequency offset, while the CS amplifier shows more asymmetry at a high frequency offset. The magnitude of the product asymmetry in the CS amplifier can be significantly higher than the CG amplifier. Methods of mitigating asymmetry are suggested for both CG and CS amplifiers. A 65 nm Si CMOS technology is used for the simulation verification of the results derived in this paper. View full abstract»

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  • A Phase and Amplitude Tunable Quadrature LC Oscillator: Analysis and Design

    Publication Year: 2011 , Page(s): 677 - 689
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2949 KB) |  | HTML iconHTML  

    This paper presents a new analytical approach to extract closed form equations for phase and amplitude imbalances raised from mismatches between two LC-tanks in quadrature oscillators. For more generality, we considered different coupling factors for the two coupled oscillators. This makes our analysis so general that we could design a phase and amplitude tunable quadrature oscillator accordingly. We show that choosing appropriate inversely proportional coupling factors makes it possible to have exactly zero phase and amplitude errors. Choosing so does not have any impacts on phase noise; indeed, the trade-off between phase noise and phase error in coupled quadrature oscillators has been broken here. We show that using differential stages for tuning tail currents of oscillating stages can somehow implement the inversely proportional coupling factors. Tuning the phase and amplitude errors, the frequency does not change and power consumption remains constant too; these are the advantages of the proposed circuit. The theoretical results and proposed quadrature oscillator are evaluated and confirmed through simulations using TSMC 0.18 model technology on a 5-GHz quadrature oscillator with current consumption of 4.2 mA at 1.8 V supply voltage. View full abstract»

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  • Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

    Publication Year: 2011 , Page(s): 690 - 698
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1766 KB) |  | HTML iconHTML  

    This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (ΣΔ) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple flnite impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the ΣΔ loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order ΣΔ modulators. View full abstract»

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  • A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation

    Publication Year: 2011 , Page(s): 699 - 710
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2764 KB) |  | HTML iconHTML  

    The benefits of using “current feedback” in instrumentation amplifier (IA) design are well known. In this paper, we analyze the mismatch mechanisms, both random and systematic types, which influence the common-mode rejection ratio (CMRR) performance of the local current feedback IA topology. We derive analytical expressions for the common-mode gain frequency response due to random mismatches (transconductance, drain-source conductance and parasitic capacitance) and verify the integrity of the analysis through simulation. To address the systematic mismatch in the drain capacitance of the input pair transistors, we employ capacitive neutralization and verify its effectiveness in practice from the fabricated IA chip samples in a 0.35- CMOS process technology. The measured average common-mode gain improvement for the 20 fabricated samples employing our neutralization technique is about 20 dB at 2 MHz ( 3 dB bandwidth). When taking into account the differential gain response (33.7 dB), the average CMRR of the neutralized IA at 2 MHz exceeds 90 dB. The IA occupies an area of 0.068 and dissipates 0.85 mW from a 3-V power supply. The circuit is intended for a wideband bioimpedance spectroscopy application. View full abstract»

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  • Energy-Saving Cooperative Spectrum Sensing Processor for Cognitive Radio System

    Publication Year: 2011 , Page(s): 711 - 723
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3836 KB) |  | HTML iconHTML  

    Cooperative spectrum sensing has recently become an important research topic for cognitive radio systems because it solves the hidden terminal problem in single-user spectrum sensing. However, idle cognitive users must consume massive spectrum sensing energy for one operating cognitive user. This characteristic reduces the attraction of the cooperative spectrum sensing technique in practical cognitive radio systems. Therefore, this paper develops a partial spectrum sensing algorithm with decision result prediction (DRP) and decision result modification (DRM) techniques to reduce the cooperative spectrum sensing energy. This study also designs and implements an energy-saving spectrum sensing processor for cognitive radio systems. The proposed cooperative spectrum sensing chip reduces energy consumption by about 64% for one fast Fourier transform (FFT) spectrum sensing calculation. For any given specified spectrum detection time, the proposed chip could also improve the detection performance compared to the traditional FFT spectrum sensing. View full abstract»

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  • Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories

    Publication Year: 2011 , Page(s): 724 - 736
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2916 KB) |  | HTML iconHTML  

    Novel nonvolatile universal memory technology is essential for providing required storage for nanocomputing. As a potential contender for the next-generation memory, the recently found "the missing fourth circuit element," memristor, has drawn a great deal of research interests. In this paper, by starting from basic memristor device equations, we develop a comprehensive set of properties and design equations for memristor based memories. Our analyses are specifically targeting key electrical memristor device characteristics relevant to memory operations. Using our derived properties, we investigate the design of read and write circuits and analyze important data integrity and noise-tolerance is sues. View full abstract»

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  • Two-Dimensional Partially Differential Cepstrum and Its Applications on Filter Stabilization and Phase Unwrapping

    Publication Year: 2011 , Page(s): 737 - 745
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2669 KB) |  | HTML iconHTML  

    A new type of differential cepstrum (DC) named as partially DC (PDC) is introduced. While compared with the previously defined DC, the PDC saves half the computational complexity since only one dimension of the partial derivative is considered. Nevertheless, for the calculation of the complex cepstrum (CC), using the PDC avoids the phase-unwrapping routine as well. One application is to construct the minimum-phase sequence from a mixed-phase one through a windowing technique, which can be further applied to filter stabilization. Another application is performing phase unwrapping on 2-D phase data to which we propose a much simpler technique using the PDC. These applications can be implemented in a more efficient and convenient way with the PDC than with the traditional DC. View full abstract»

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  • Design of 2-D Wideband Circularly Symmetric FIR Filters by Multiplierless High-Order Transformation

    Publication Year: 2011 , Page(s): 746 - 754
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2216 KB) |  | HTML iconHTML  

    In this paper, we modify the original McClellan transformation to a th-order version, and on the basis of the th-order McClellan transformation, we propose two high-order transformations for designing circularly symmetric wideband two-dimensional (2-D) digital FIR filter. The circularity of the resulting 2-D filters designed by our transformations is comparable to those 2-D filters designed by the other methods; however, the existing methods for circularly symmetric design cannot obtain a 2-D filter by the application of a single transformation on the 1-D filter response. By using the proposed transformations, in a single transformation on the 1-D filter, we can easily obtain the circularly symmetric 2-D digital FIR filter over a wide range of cutoff frequencies. Besides, with our approach, neither optimization procedure nor any computation is needed to obtain the transformation. Furthermore, since the implementations of the transformations are all multiplierless, the resulting 2-D filter has the same number of multipliers with the 1-D prototype filter. In the narrowband case, the 2-D transition width is shown to be narrower by a factor of about (and ) than the transition width of the 1-D prototype filter. This means that the filter length required in the prototype filter is shorter than that using the existing methods. View full abstract»

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  • Multidimensional DFT IP Generator for FPGA Platforms

    Publication Year: 2011 , Page(s): 755 - 764
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1304 KB) |  | HTML iconHTML  

    Multidimensional (MD) discrete Fourier transform (DFT) is a key kernel algorithm in many signal processing applications. In this paper we describe an MD-DFT intellectual property (IP) generator and a bandwidth-efficient MD DFT IP for high performance implementations of 2-D and 3-D DFT on field-programmable gate array (FPGA) platforms. The proposed architecture is generated automatically and is based on a decomposition algorithm that takes into account FPGA resources and the characteristics of off-chip memory access, namely, the burst access pattern of the synchronous dynamic RAM (SDRAM). The IP generator has been integrated into an in-house FPGA development platform, AlgoFLEX, for easy verification and fast integration. The corresponding 2-D and 3-D DFT architectures have been ported onto the BEE3 board and their performance measured and analyzed. The results shows that the architecture can maintain the maximum memory bandwidth throughout the whole procedure while avoiding matrix transpose operations used in most other MD DFT implementations. To further enhance the performance, the proposed architecture is being ported onto the newly released Xilinx ML605 board. The simulation results show that 2 K × 2 K images with complex 64-bit precision can be processed in less than 27 ms. View full abstract»

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  • Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider—Part II: Design Methodology

    Publication Year: 2011 , Page(s): 765 - 776
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2827 KB) |  | HTML iconHTML  

    An intuitive approach to analyze the behavior of an Injection-Locked Frequency Divider was presented in Part I of this work; that paper provided insight into the locking behavior in the valid design area of the circuit. In this paper, we present a rigorous design methodology which provides a closed form equation showing where the locking range is wider. Theoretical predictions of the locked regions are verified by simulations of the circuit in Spectre RF using 0.35-CMOS technology models. View full abstract»

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  • A 32 ,\times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput

    Publication Year: 2011 , Page(s): 777 - 790
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2723 KB) |  | HTML iconHTML  

    This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 × 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 × 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 CMOS technology, occupies 4.3 × 5.4 and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate. View full abstract»

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  • An Asynchronous Spike Event Coding Scheme for Programmable Analog Arrays

    Publication Year: 2011 , Page(s): 791 - 799
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1965 KB) |  | HTML iconHTML  

    This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-μm CMOS technology are presented. View full abstract»

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  • Adaptive Unknown-Input Observers-Based Synchronization of Chaotic Systems for Telecommunication

    Publication Year: 2011 , Page(s): 800 - 812
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1532 KB) |  | HTML iconHTML  

    We propose a robust adaptive chaotic synchronization method based on unknown-input observers for master-slave synchronization of chaotic systems, with application to secured communication. The slave system is modelled by an unknown input observer in which, the unknown input is the transmitted information. As in the general observer-based synchronization paradigm, the information is recovered if the master and slave systems robustly synchronize. In the context of unknown-input observers, this is tantamount to estimating the master's states and the unknown inputs. The set-up also considers the presence of perturbations in the chaotic transmitter dynamics and in the output equations (the transmitted signal). That is, the estimator (slave system) must synchronize albeit noisy measurements and reject the effect of perturbations on the transmitter dynamics. We provide necessary and sufficient conditions for synchronization to take place. To highlight our contribution, we also present some simulation results with the purpose of comparing the proposed method to classical adaptive observer-based synchronization (without disturbance rejection). It is shown that additive noise is perfectly canceled and the encoded message is well recovered despite the perturbations. View full abstract»

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  • Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization

    Publication Year: 2011 , Page(s): 813 - 826
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3071 KB) |  | HTML iconHTML  

    The advent of multiple-input-multiple-output (MIMO) techniques has resulted in the generation of new design problems, especially in the baseband processing task of symbol detection. Lattice reduction (LR)-aided detection techniques have emerged as a low-complexity method to achieve the same diversity as the maximum likelihood detector. In this article we explore efficient hardware realization of the complex Lenstra, Lenstra, Lovász (CLLL) LR algorithm. We accomplish this task by first developing an understanding of the complex relationship between algorithm and hardware considerations. After proposing hardware-motivated algorithm modifications, we apply this understanding to the design of a 4 × 4 CLLL processor for MIMO detection. Hardware realization results on a Xilinx XC4VLX80-12 FPGA demonstrate that the CLLL processor has a throughput of over 3.5 M channel matrices per second, outperforming previously disclosed hardware realizations. In addition, the algorithm modifications and design procedures that we propose are easily applied to larger MIMO system sizes. View full abstract»

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  • Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis

    Publication Year: 2011 , Page(s): 827 - 838
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2090 KB) |  | HTML iconHTML  

    This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of fast Fourier transforms (FFTs) for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design tradeoffs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65 nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead. View full abstract»

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  • A High-Throughput LDPC Decoder Architecture With Rate Compatibility

    Publication Year: 2011 , Page(s): 839 - 847
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    This paper presents a high-throughput decoder architecture for rate-compatible (RC) low-density parity-check (LDPC) codes which supports arbitrary code rates between the rate of mother code and 1. Puncturing techniques are applied to produce different rates for quasi-cyclic (QC) LDPC codes with dual-diagonal parity structure. Simulation results show that our selected puncturing scheme only introduces the BER performance degradation of less than 0.2 dB, compared with the dedicated codes for different rates specified in the IEEE 802.16e (WiMax) standard. Subsequently, parallel layered decoding architecture (PLDA) is employed for high-throughput decoder design. While the original PLDA is lack of rate flexibility, the problem is solved gracefully by incorporating the puncturing scheme. As a case study, an RC-LDPC decoder based on the rate-1/2 WiMax LDPC code is implemented in the CMOS 65-nm process. The clock frequency is 1.1 GHz, and the synthesis core area is 1.96 mm2. The decoder can achieve an input throughput of 1.28 Gb/s at ten iterations and supports any rate between 1/2 and 1. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2011 , Page(s): 848
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2011 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras