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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 8 • Date Aug. 2010

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Displaying Results 1 - 25 of 43
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2010 , Page(s): C2
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  • Design of X -Band and Ka -Band Colpitts Oscillators Using a Parasitic Cancellation Technique

    Publication Year: 2010 , Page(s): 1817 - 1828
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1355 KB) |  | HTML iconHTML  

    An X-band and two Ka-band monolithic microwave integrated circuit (MMIC) common drain Colpitts oscillators using a parasitic cancellation technique are designed and fabricated in a 0.2-μm GaAs pHEMT technology with a fT of 60 GHz. The parasitic cancellation technique significantly improves the negative resistance and increases the maximum operating frequency, which is suitable for microwave and millimeter-wave applications. An in-depth theoretical analysis of the Miller effect and insights in the behavior of the input impedance with the parasitic cancellation are provided. The effect of the Q-factor of the inductor used in the cancellation, and the impact of the parasitic cancellation technique on phase noise and frequency tuning range are analyzed and discussed in detail. The X-band design has a measured phase noise of -117.5 dBc/Hz at 1 MHz offset with an output power of -9.3 dBm . The first Ka-band design has a measured phase noise of -94 dBc/Hz at 1 MHz offset with an output power of +0.2 dBm. The second Ka-band design providing more flexibility has a measured phase noise of -98.5 dBc/Hz at 1 MHz offset with an output power of + 0.3 dBm. The two Ka-band designs achieve very high fOSC/fT ratios and also demonstrate performance comparable to the best previously published oscillators in a similar frequency range. View full abstract»

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  • An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

    Publication Year: 2010 , Page(s): 1829 - 1837
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1337 KB) |  | HTML iconHTML  

    This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 × 50 μm2 and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step. View full abstract»

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  • Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

    Publication Year: 2010 , Page(s): 1838 - 1847
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2437 KB) |  | HTML iconHTML  

    We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed sensor is 2.3× better than the previous sensor reported in the literature which utilizes above-threshold operation. To further improve the sensitivity of the proposed sensor, an amplifier stage working in the sub-threshold region is designed. This enables 4× additional increase in sensitivity. A test-chip containing an array of 128 PMOS and 128 NMOS devices has been fabricated in 65-nm bulk CMOS process technology. A total of 28 dies across the wafer have been fully characterized and the random threshold voltage variations are reported here. View full abstract»

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  • The Transimpedance Limit

    Publication Year: 2010 , Page(s): 1848 - 1856
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    The transimpedance limit describes the maximum transimpedance that a transimpedance amplifier (TIA) can attain for a given bandwidth and technology. We analyze and compare this limit for a wide variety of TIA topologies thus exposing their relative merits. The topologies considered are the shunt-feedback TIA with single and multistage amplifier, the shunt-feedback TIA with feedback capacitor, the shunt-feedback TIA followed by a post amplifier, the shunt-feedback TIA with a current amplifier, the common-base/gate feedforward TIA, the shunt-feedback TIA with a common-base/gate input stage, and the shunt-feedback TIA with a regulated-cascode input stage. The analysis includes a discussion of the conditions under which the limit is realizable. View full abstract»

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  • Practical Approach to Programmable Analog Circuits With Memristors

    Publication Year: 2010 , Page(s): 1857 - 1864
    Cited by:  Papers (105)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB) |  | HTML iconHTML  

    We suggest an approach to use memristors (resistors with memory) in programmable analog circuits. Our idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor's states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor-based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us. View full abstract»

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  • Control of MEMS Vibration Modes With Pulsed Digital Oscillators: Part I—Theory

    Publication Year: 2010 , Page(s): 1865 - 1878
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    The aim of this paper is to show that it is possible to excite selectively different mechanical resonant modes of a MEMS structure using pulsed digital oscillators (PDOs). This can be done by simply changing the working parameters of the oscillator, namely its sampling frequency or its feedback filter. A set of iterative maps is formulated to describe the evolution of the spatial modes between two sampling events in PDOs. With this lumped model, it is established that under some circumstances PDO bitstreams related to only one of the resonances can be obtained, and that in the anti-oscillation regions of the PDO the mechanical energy is absorbed into the electrical domain on average. The possibility of selecting for a given resonant frequency the oscillation and anti-oscillation behavior allows one to obtain oscillations at any given resonant mode of the MEMS structure. View full abstract»

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  • Control of MEMS Vibration Modes With Pulsed Digital Oscillators—Part II: Simulation and Experimental Results

    Publication Year: 2010 , Page(s): 1879 - 1890
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3225 KB) |  | HTML iconHTML  

    This paper extends our previous work on the selective excitation of mechanical vibration modes in MEMS devices using pulsed digital oscillators (PDOs). It begins by presenting extensive simulation results using the set of iterative maps that model the system and showing that it is possible to activate two or three spatial modes (resonances) of the mechanical structure with a PDO. The second part of this paper presents experimental results corroborating the theory and simulation results. It is shown that it is possible to separately excite vibration modes of the device by setting a few parameters of the PDO structure such as the sampling frequency and the sign of the feedback loop. View full abstract»

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  • Recombination of Envelope and Phase Paths in Wideband Polar Transmitters

    Publication Year: 2010 , Page(s): 1891 - 1904
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1348 KB) |  | HTML iconHTML  

    We investigate the recombination of discrete-time envelope and phase/frequency components of a polar transmitter, which is based here on an all-digital phase-locked loop (ADPLL) with wideband modulation capability and a digitally controlled power amplifier (DPA). A unified discrete/continuous-time analysis is introduced for the development of the interpolative transfer characteristics of the envelope and phase paths that allows their recombination to be studied in the continuous-time domain of the DPA radio-frequency output. The nonlinear recombination of the polar components in the DPA is analytically investigated in the context of a proposed characterization technique that utilizes single-tone envelope and phase signals, and conclusions on the optimal architecture of a wideband ADPLL-based polar transmitter are drawn. The harmonic distortion results obtained in the context of the proposed characterization technique effectively highlight the performance of the polar transmitter when it is driven with the wideband baseband envelope and phase-modulating signals of today's high-data-rate digital communication systems, such as wideband code-division multiple access and beyond. View full abstract»

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  • Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

    Publication Year: 2010 , Page(s): 1905 - 1913
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1842 KB) |  | HTML iconHTML  

    This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant. View full abstract»

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  • Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional- N PLLs

    Publication Year: 2010 , Page(s): 1914 - 1924
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) noise, including its effect on the in-band phase noise. The thermal device noise of the CP and the turn-on time of the CP output current are found to be limiting the in-band phase noise of state-of-the-art synthesizers. Device noise considerations for bipolar transistors and MOSFETs suggest the use of CMOS-only CPs, even in BiCMOS technologies. We present a noise-optimized CMOS CP specifically designed for a dual-loop PLL architecture using two CPs. This PLL architecture keeps the dc output voltage of the noise-relevant CP and the phase-noise spectrum constant, regardless of temperature variations. View full abstract»

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  • Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters

    Publication Year: 2010 , Page(s): 1925 - 1934
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1266 KB) |  | HTML iconHTML  

    We propose a technique that enables the study of weak loop filter nonlinearities in a class of continuous-time delta-sigma modulators. The technique can easily be implemented in a tool intended to simulate discrete-time modulators with linear loop filters, thereby significantly reducing the simulation time. Thanks to this technique, the utility of the Schreier Delta-Sigma toolbox can be extended to include weakly nonlinear effects in the loop filter, thus enabling the architectural exploration of alternate loop filter and operational amplifier (opamp) topologies. The results from the use of our technique are compared to those obtained using a circuit simulator, and good agreement is seen. View full abstract»

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  • Theory of Flying-Adder Frequency Synthesizers—Part I: Modeling, Signals' Periods and Output Average Frequency

    Publication Year: 2010 , Page(s): 1935 - 1948
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to gener- - ate numerous examples illustrating the developed theory. View full abstract»

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  • Theory of Flying-Adder Frequency Synthesizers—Part II: Time- and Frequency-Domain Properties of the Output Signal

    Publication Year: 2010 , Page(s): 1949 - 1963
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (766 KB) |  | HTML iconHTML  

    This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts. Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all the FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to g- - enerate numerous examples, illustrating the developed theory. View full abstract»

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  • Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier

    Publication Year: 2010 , Page(s): 1964 - 1972
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1847 KB) |  | HTML iconHTML  

    A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ. View full abstract»

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  • Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator

    Publication Year: 2010 , Page(s): 1973 - 1982
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    This paper presents the design of a low-voltage ultralow-power relaxation oscillator without external components. The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems. A detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results. The oscillator operates at a typical frequency of 3.3 kHz and consumes 11 nW from a 1-V supply at room temperature, and a temperature drift of less than 500 ppm/°C is achieved over the temperature range of -20°C to 80°C. An efficient design implementation has resulted in a cell area of 0.1 mm2 in a standard 0.35- μm digital CMOS technology. View full abstract»

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  • Available Energy and Passivity of First-Order LLTI One-Ports

    Publication Year: 2010 , Page(s): 1983 - 1992
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    The energy behavior of first-order linear lumped time-invariant one-ports is thoroughly investigated, starting from the definition of available energy introduced by Wyatt in 1981 and exploiting the calculus of variations approach. First, all the extrema of the energy delivered from these components over finite time intervals are identified and evaluated. Then, available energy and passivity are inferred by comparing these results on the nonnegative time half-axis. The case of reducible one-ports, which is beyond the traditional criterion based on the theory of positive-real rational functions, is also treated. Two numerical circuital examples are used throughout this paper to illustrate the theoretical results obtained. View full abstract»

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  • A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications

    Publication Year: 2010 , Page(s): 1993 - 2005
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1159 KB) |  | HTML iconHTML  

    A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the CG transistor. This leads to an LNA with higher gain and lower noise figure (NF) compared with the conventional CG-CS LNA, particularly under low power and voltage constraints. By adjusting the local open-loop gain, the NF can be optimized by distributing the power consumption among transistors and resistors based on their contribution to the NF. The optimal value of the local open-loop gain can be obtained by taking into account the effect of phase shift at high frequency. The linearity is improved by employing two types of distortion-cancelling techniques. Fabricated in a 0.13-μm RF CMOS process, the LNA achieves a voltage gain of 19 dB and an NF of 2.8-3.4 dB over a 3-dB bandwidth of 0.2-3.8 GHz. It consumes 5.7 mA from a 1-V supply and occupies an active area of only 0.025 mm2. View full abstract»

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  • Stability and Operation of Injection-Locked Regenerative Frequency Dividers

    Publication Year: 2010 , Page(s): 2006 - 2019
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1469 KB) |  | HTML iconHTML  

    Injection-locked regenerative frequency dividers can achieve a fractional division ratio similar to regenerative frequency dividers and can provide quadrature output phases. An analysis of the steady-state operation, stability, and phase noise of injection-locked regenerative frequency dividers is presented. In addition, two-stage ring oscillators (based on negative-resistance delay cells) are studied, and their steady-state free-running operation and injection-locked behavior are investigated. Simulation results based on the equations derived in this paper are compared with circuit simulations to examine the accuracy of our analysis, which is quantified in different parts of this paper. View full abstract»

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  • Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems

    Publication Year: 2010 , Page(s): 2020 - 2031
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2095 KB) |  | HTML iconHTML  

    This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits. View full abstract»

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  • Efficient Soft Error-Tolerant Adaptive Equalizers

    Publication Year: 2010 , Page(s): 2032 - 2040
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1137 KB) |  | HTML iconHTML  

    Soft errors are becoming an increasingly important issue for circuit reliability. Traditional techniques to protect against soft errors, like triple modular redundancy (TMR), have a large cost in terms of area and power. This has motivated the development of specific protection techniques for various types of circuits. In this paper, techniques to protect adaptive filters are presented, which provide reasonable reliability with reduced cost and power consumption. An adaptive equalizer case study is used to discuss and evaluate the proposed techniques in terms of both protection and cost. View full abstract»

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  • An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization

    Publication Year: 2010 , Page(s): 2041 - 2052
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an N number of logic gates, the proposed mathematical program has reduced the number of variables to N+1, in comparison to 7N+1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-μm CMOS technology. View full abstract»

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  • Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

    Publication Year: 2010 , Page(s): 2053 - 2065
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1159 KB) |  | HTML iconHTML  

    Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology. View full abstract»

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  • ULPFA: A New Efficient Design of a Power-Aware Full Adder

    Publication Year: 2010 , Page(s): 2066 - 2074
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras