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# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
| PDF (39 KB)
• ### Generalized Time- and Transfer-Constant Circuit Analysis

Publication Year: 2010, Page(s):1105 - 1121
Cited by:  Papers (15)
| | PDF (554 KB) | HTML

The generalized method of time and transfer constants is introduced. It can be used to determine the transfer function to the desired level of accuracy in terms of time and transfer constants of first-order systems using exclusively low frequency calculations. This method can be used to determine the poles and zeros of circuits with both inductors and capacitors. An inductive proof of this general... View full abstract»

• ### A High-Performance Fast Switching Charge Dump Assisted Class-$K^{\ast}$Audio Amplifier

Publication Year: 2010, Page(s):1122 - 1133
Cited by:  Papers (3)
| | PDF (2040 KB) | HTML

A new Class-K*audio amplifier with high-power efficiency and high fidelity is integrated in a 0.35-μm CMOS process. It proposes a new topology connected Class-D amplifier with fast-switching charge-dump (FSCD) amplifier in parallel. The integration of the amplifier requires neither analog buffer amplifier nor a complex compensation circuit needed in hybrid audio amplifier (Class-K). The FSC... View full abstract»

• ### FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range

Publication Year: 2010, Page(s):1134 - 1142
Cited by:  Papers (17)  |  Patents (6)
| | PDF (1050 KB) | HTML

The first FPGA multiple channel digital-to-time converter, or digital pulse generator, is proposed to further extend FPGA applications into analog domain. Based on vernier principle, the effective resolution is made equivalent to the period difference of two phase-locked loop (PLL) outputs. The finer than ever DTC resolution of 1.58 ps is achieved with an Altera Stratix III FPGA chip. The DNL and ... View full abstract»

• ### A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation

Publication Year: 2010, Page(s):1143 - 1153
Cited by:  Papers (21)
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An analog circuit for implementing pulse-coupled neural networks (PCNNs) in very-large-scale integration (VLSI) hardware has been developed using the Neuron-MOS (νMOS) technology. PCNNs are biologically inspired models having powerful ability for image feature generation. With the νMOS technology, weighted sum of multiple input signals, which is an essential of PCNNs, is implemented simply by the ... View full abstract»

• ### Current Mode Image Sensor With Two Transistors per Pixel

Publication Year: 2010, Page(s):1154 - 1165
Cited by:  Papers (24)
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A linear current mode active pixel sensor for low fixed-pattern noise imaging is presented. The photo pixel is composed of a photodiode, a reset transistor, and a transconductance amplifier transistor. The address switch transistor is placed outside the pixel. The increased linearity of the pixel current coupled with current mode difference double sampling greatly reduces spatial variations across... View full abstract»

• ### Combining the Standard Histogram Method and a Stimulus Identification Algorithm for A/D Converter INL Testing With a Low-Quality Sine Wave Stimulus

Publication Year: 2010, Page(s):1166 - 1174
Cited by:  Papers (11)
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This paper proposes combining the standard histogram method with a stimulus identification algorithm in order to test the integral nonlinearity (INL) of a high-resolution analog-to-digital (A/D) converter without a high-quality sine wave. The major problems in the two techniques are explained in order to appreciate the benefits of the combination. The increased INL estimation accuracy is verified ... View full abstract»

• ### Resonant-Inductive Degeneration for Manifold Improvement of Phase Noise in Bipolar LC-Oscillators

Publication Year: 2010, Page(s):1175 - 1186
Cited by:  Papers (6)
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Resonant-inductive degeneration of bias current source is described in this paper as a method for a manifold improvement of phase noise in inductance-capacitance (<i>LC</i>) voltage- controlled oscillators. For the verification of this phase-noise reduction method, a test bipolar <i>LC</i>-oscillator has been designed using a phase-noise model obtained from the spectral noi... View full abstract»

• ### Phase Noise inLCOscillators: A Phasor-Based Analysis of a General Result and of Loaded$Q$

Publication Year: 2010, Page(s):1187 - 1203
Cited by:  Papers (71)  |  Patents (1)
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Recent work by Bank, and Mazzanti and Andreani has offered a general result concerning phase noise in nearly-sinusoidal inductance-capacitance (LC) oscillators; namely that the noise factor of such oscillators (under certain achievable conditions) is largely independent of the specific operation of individual transistors in the active circuitry. Both use the impulse sensitivity function (IS... View full abstract»

• ### Process and Temperature Compensation for RF Low-Noise Amplifiers and Mixers

Publication Year: 2010, Page(s):1204 - 1211
Cited by:  Papers (22)
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Temperature and process variations have become key issues in the design of integrated circuits using deep submicron technologies. In RF front-end circuitry, many characteristics must be compensated in order to maintain acceptable performance across all process corners and throughout the temperature range. This paper proposes a new technique consisting of a compensation circuit that adapts and gene... View full abstract»

• ### A Gaussian Pulse Generator for Millimeter-Wave Applications

Publication Year: 2010, Page(s):1212 - 1220
Cited by:  Papers (6)
| | PDF (1446 KB) | HTML

A millimeter wave (MMW) pulse generator with Gaussian-like envelope is presented. The pulse generator is based on a Gaussian-envelope signal which modulates a sinusoidal carrier. Besides providing spectral purity at high frequency, the proposed circuit also exhibits high flexibility. Indeed, it is suitable for the 57-66-GHz frequency band, but also for the UWB applications in 3-10 GHz, thanks to i... View full abstract»

• ### Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-$N$PLLs

Publication Year: 2010, Page(s):1221 - 1230
Cited by:  Papers (10)  |  Patents (1)
| | PDF (1380 KB) | HTML

A recent charge pump linearization technique demonstrated 8 dB reduction in spurious tones caused by charge pump current mismatch in delta-sigma fractional-Nphase locked loops. In this paper, two purely digital mismatch shaping techniques are proposed to modify and further improve the charge pump linearization technique. Both the techniques suppress spurious tones by randomizing the residua... View full abstract»

• ### Time Division Multiplexing Front-Ends for Multiantenna Integrated Wireless Receivers

Publication Year: 2010, Page(s):1231 - 1243
Cited by:  Papers (14)
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The approach of time division multiplexing (TDM) within an integrated wireless receiver to reduce the power, area and cost of multiple antenna receivers is studied. A solution is proposed to address the cross-interference between multiplex channels that affected previous attempts at TDM for multiple receive antennas. Detailed analysis from a radio system viewpoint is provided for when TDM is used ... View full abstract»

• ### The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter

Publication Year: 2010, Page(s):1244 - 1254
Cited by:  Papers (25)
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This paper presents an open-loop design method for fast-settling three-stage class-A amplifiers. Specifically, using the open-loop damping factor as a design parameter, the presented method delivers robust settling performance of a third-order system in the presence of process and component variation. As an illustration of the proposed approach, we show Spice simulation results of a nested-Miller-... View full abstract»

• ### Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters

Publication Year: 2010, Page(s):1255 - 1264
Cited by:  Papers (18)
| | PDF (452 KB) | HTML

In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated... View full abstract»

• ### Circuit-Based Characterization of Device Noise Using Phase Noise Data

Publication Year: 2010, Page(s):1265 - 1272
Cited by:  Papers (4)
| | PDF (1076 KB) | HTML

A circuit-based device noise characterization technique is introduced which uses phase noise data to estimate the power spectral density (PSD) of high-frequency noise in MOSFETs. To apply this technique to a typical CMOS process, an oscillator structure is introduced which provides a predictable phase noise level for a given device noise PSD. The analytical equations governing the phase noise of t... View full abstract»

• ### Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design

Publication Year: 2010, Page(s):1273 - 1286
Cited by:  Papers (25)
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In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading... View full abstract»

• ### Reduction of Substrate Noise in Sub Clock Frequency Range

Publication Year: 2010, Page(s):1287 - 1297
Cited by:  Papers (2)
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We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the curren... View full abstract»

• ### A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Publication Year: 2010, Page(s):1298 - 1311
Cited by:  Papers (19)
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Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by... View full abstract»

• ### Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error

Publication Year: 2010, Page(s):1312 - 1325
Cited by:  Papers (54)  |  Patents (2)
| | PDF (1652 KB) | HTML

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this pap... View full abstract»

• ### Minimax Design of IIR Digital Filters Using Iterative SOCP

Publication Year: 2010, Page(s):1326 - 1337
Cited by:  Papers (31)
| | PDF (641 KB) | HTML

In this paper, a novel method for IIR digital filter design using iterative second-order cone programming (SOCP) is proposed under the minimax criterion. The convex relaxation technique is utilized to transform the original nonconvex design problem into an SOCP problem. By solving the relaxed problem, the lower and upper bounds on the optimal value of the original problem can be obtained. In order... View full abstract»

• ### Fundamental Properties of Non-Negative Impulse Response Filters

Publication Year: 2010, Page(s):1338 - 1347
Cited by:  Papers (9)
| | PDF (394 KB) | HTML

This paper provides insights into some fundamental properties of non-negative impulse response (NNIR) digital filters. In particular, performance restrictions in the frequency domain due to the non-negativity constraint are investigated. It is shown that the gain drop in the frequency response near zero frequency affects the response over the entire frequency spectrum. The passband and stopband ga... View full abstract»

• ### Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time

Publication Year: 2010, Page(s):1348 - 1357
| | PDF (1113 KB) | HTML

A CMOS ratio-memory cellular nonlinear network (RMCNN) requiring no elapsed time is proposed. The correlations between any two neighboring cells are stored in the memories. The ratio weights of each cell are generated through a comparison of the four correlations around one cell with the mean value of these four correlations. With this method, the elapsed time required by the previously existing R... View full abstract»

• ### Time-Oriented Synthesis for aWTAContinuous-Time Neural Network Affected by Capacitive Cross-Coupling

Publication Year: 2010, Page(s):1358 - 1370
Cited by:  Papers (11)
| | PDF (600 KB) | HTML

A continuous time neural network built with nonlinear amplifiers which selects the largest item of a list (WTA) is considered. The network receives and processes lists admitted one by one. If the processing and resetting times are imposed, our paper gives a method to find the circuit parameters assuring a correct operation. We take into account the capacitive coupling between input terminal... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK