# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
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• ### Spectral Analysis of Phase Noise in Bipolar LC-Oscillators—Theory, Verification, and Design

Publication Year: 2010, Page(s):737 - 751
Cited by:  Papers (10)
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Interpretation of phase-noise generating mechanism in oscillators relies on approximate and numerical calculations for analysis, and simulation tools for synthesis. In this paper, a comprehensive, yet intuitive, phase-noise model is derived as a function of oscillator circuit parameters, suiting both analysis and synthesis of oscillators. Contributions of all noise sources to the phase noise of bi... View full abstract»

• ### Full 360$^{circ }$ Vector-Sum Phase-Shifter for Microwave System Applications

Publication Year: 2010, Page(s):752 - 758
Cited by:  Papers (20)  |  Patents (3)
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An innovative vector-sum phase shifter with a full 360° variable phase-shift range is proposed and experimentally demonstrated in this paper. It employs an active balun and a very high-speed CMOS operational transconductance amplifier (OTA) integrator to generate the four quadrature basis vector signals. The fabricated chip operates in the 2-3 GHz, it exhibits an average insertion gain of 1.5... View full abstract»

• ### Theory and Bandwidth Enhancement of Cascaded Double-Stage Distributed Amplifiers

Publication Year: 2010, Page(s):759 - 772
Cited by:  Papers (8)
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Theoretical analysis and bandwidth enhancement of the cascaded double-stage distributed amplifiers (CDSDA) are presented. The characteristics of the general cascaded multi-stage distributed amplifiers (CMSDA) with open idle drain terminations at intersections for a high gain are investigated with lossy artificial lumped line models. This reveals the inherent bandwidth limitation of the CMSDA due t... View full abstract»

• ### A Wideband Low Power Low-Noise Amplifier in CMOS Technology

Publication Year: 2010, Page(s):773 - 782
Cited by:  Papers (28)
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A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a low-noise amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband low-noise amplifier with a b... View full abstract»

• ### Far-Field Acoustic Source Localization and Bearing Estimation Using $SigmaDelta$ Learners

Publication Year: 2010, Page(s):783 - 792
Cited by:  Papers (8)
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Localization of acoustic sources using miniature microphone arrays poses a significant challenge due to fundamental limitations imposed by the physics of sound propagation. With sub-wavelength distances between the microphones, resolving acute localization cues become difficult due to precision artifacts. In this paper we propose a framework which overcomes this limitation by integrating signal-me... View full abstract»

• ### A Low-Power Quadrature VCO and Its Application to a 0.6-V 2.4-GHz PLL

Publication Year: 2010, Page(s):793 - 802
Cited by:  Papers (38)  |  Patents (1)
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A novel circuit topology of the quadrature voltage-controlled oscillator (QVCO) is presented in this paper for low-voltage and low-power applications. With the antiphase coupling provided by the MOSFETs in a passive mode, quadrature output phases can be generated at minimum power consumption while maintaining desirable circuit performance in terms of phase error and phase noise. Based on the propo... View full abstract»

• ### A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks

Publication Year: 2010, Page(s):803 - 813
Cited by:  Papers (3)
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A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research . The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/divi... View full abstract»

• ### Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals

Publication Year: 2010, Page(s):814 - 822
Cited by:  Papers (30)
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Ternary content addressable memory (TCAM) is more susceptible to soft errors than static random access memory (SRAM). The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. The tight structural coupling of TCAM comparison circuits and memory cells does not allow for an interleaving design scheme in mitigating soft errors. Regu... View full abstract»

• ### Efficient Reverse Converter Designs for the New 4-Moduli Sets ${2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1}$ and ${2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1}$ Based on New CRTs

Publication Year: 2010, Page(s):823 - 835
Cited by:  Papers (60)
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In this paper, we introduce two new 4-moduli sets {2n-1, 2n, 2n+1, 22n+1-1} and {2n-1, 2n+1, 22n, 22n+1} for developing efficient large dynamic range (DR) residue number systems (RNS). These moduli sets consist of simple and well-formed moduli which can result in efficient implementation of the reverse converte... View full abstract»

• ### Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders

Publication Year: 2010, Page(s):836 - 849
Cited by:  Papers (11)  |  Patents (1)
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A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding and decoding. A series of implementation-oriented constraints are applied to construct architecture-aware (AA) codes by introducing algebraic structures into the parity-check matrix. The resulting AA codes... View full abstract»

• ### Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications

Publication Year: 2010, Page(s):850 - 862
Cited by:  Papers (57)
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The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more ef... View full abstract»

• ### A Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method

Publication Year: 2010, Page(s):863 - 872
Cited by:  Papers (21)
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This paper introduces a novel direct digital frequency synthesizer (DDFS) with an architecture based on the quasi-linear interpolation method (QLIP). The QLIP method is a hybrid polynomial interpolation in which the first quarter of a cosine function is approximated by two sets of linear and parabolic polynomials. The section of the cosine function that is closer to its peak is interpolated by par... View full abstract»

• ### A Low-Complexity Viterbi Decoder for Space-Time Trellis Codes

Publication Year: 2010, Page(s):873 - 885
Cited by:  Papers (6)  |  Patents (1)
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Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its gains in coding and diversity; however, its great decoding complexity makes it less promising in chip realization compared to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm and increases signif... View full abstract»

• ### Design of a Robust Multi-Channel Timing Recovery System With Imperfect Channel State Information for 10GBASE-T

Publication Year: 2010, Page(s):886 - 896
Cited by:  Papers (2)
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The interdependence among multiple channels and the interaction between timing and equalization loops bring new challenges to the design of a multi-channel symbol timing recovery (STR) system for 10GBASE-T. In addition, the nonlinear Tomlinson-Harashima precoding (THP) technique used in the 10GBASE-T system is vulnerable to the imperfect channel state information (CSI). In this paper, we address t... View full abstract»

• ### Hybrid Structures for Low-Complexity Variable Fractional-Delay FIR Filters

Publication Year: 2010, Page(s):897 - 910
Cited by:  Papers (38)
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This paper proposes a pair of new structures for implementing low-complexity odd-order and even-order variable fractional-delay (VFD) FIR filters using hybrid structures with both even-order and odd-order subfilters. For odd-order VFD filter design, the main idea is to replace the conventional even-symmetric odd-order (type-2) subfilters with the cascade of a type-2 half-delay filter and even-symm... View full abstract»

• ### A Novel Split-Radix Fast Algorithm for 2-D Discrete Hartley Transform

Publication Year: 2010, Page(s):911 - 924
Cited by:  Papers (8)
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This paper presents a fast split-radix- (2&times;2)/(8&times;8) algorithm for computing the 2-D discrete Hartley transform (DHT) of length N ??N with N = q ?? 2 m, where q is an odd integer. The proposed algorithm decomposes an N ?? N DHT into one N /2 ?? N /2 DHT and 48 N /8 ?? N /8 DHTs. It achieves an ef... View full abstract»

• ### A Robust Channel Estimator for High-Mobility STBC-OFDM Systems

Publication Year: 2010, Page(s):925 - 936
Cited by:  Papers (8)
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In this paper, a robust channel estimator for high- mobility space-time block code-orthogonal frequency division multiplexing (STBC-OFDM) systems is proposed and applied in IEEE 802.16e systems. A high-performance two-stage channel estimation method is adopted. The proposed architecture reduces computational complexity effectively and improves 85.2% of the hardware implementation. The performances... View full abstract»

• ### Bifurcation Analysis on a Multimachine Power System Model

Publication Year: 2010, Page(s):937 - 949
Cited by:  Papers (22)
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In this article bifurcation analysis of the 9 bus power system model corresponding to the Western Systems Coordinating Council is performed. In order to use standard continuation packages like MATCONT, a full ordinary differential equations model, including the corresponding dynamics of the control loops and the transmission lines, is derived. Different loading conditions are studied by using the ... View full abstract»

• ### 17th IEEE International Conference on Electronics Circuits and Systems(ICECS 2010)

Publication Year: 2010, Page(s): 950
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• ### ISCAS 2010

Publication Year: 2010, Page(s): 951
| |PDF (642 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

Publication Year: 2010, Page(s): 952
| |PDF (41 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2010, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK