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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 3 • Date March 2010

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Displaying Results 1 - 25 of 25
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2010 , Page(s): C2
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  • Herbert J. Carlin (1917-2009)

    Publication Year: 2010 , Page(s): 529
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  • Systematic Design of a Transimpedance Amplifier With Specified Electromagnetic Out-of-Band Interference Behavior

    Publication Year: 2010 , Page(s): 530 - 538
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (526 KB) |  | HTML iconHTML  

    In negative-feedback amplifier design, electromagnetic interference (EMI) behavior is usually completely disregarded. EMI can, e.g., result in detection of low-frequency envelope variations of the usually high-frequency interfering signals. If the detected signals end up in the pass band of the negative-feedback amplifier, they cannot be distinguished from the intended signal any longer, so the signal-to-error ratio (SER) is reduced. Several measures can be taken to prevent unacceptable reduction of the SER, like applying filters, chokes, etc. In this paper, however, circuit design aspects are investigated. It is assumed that interference reaches the amplifier input and that the SER has to be assured by a proper design of the negative-feedback amplifier. Since EMI is related to nonlinear distortion, it is a function of the loop gain of the negative-feedback amplifier. For a given electromagnetic (EM) environment it is therefore possible to calculate the minimum loop gain required to reduce EMI to acceptable levels without filtering. To illustrate this systematic design method a transimpedance amplifier is designed and built to properly function in interfering field strengths up to 30 V/m. Experimental results are in good agreement with theory. View full abstract»

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  • Transient Charge Feedforward Driver for High-Speed Current-Mode Data Driving in Active-Matrix OLED Displays

    Publication Year: 2010 , Page(s): 539 - 547
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1142 KB) |  | HTML iconHTML  

    A transient charge feedforward driver (TCFD) is presented for high-speed current-mode data driving in active-matrix organic LED (AMOLED) displays. In order to provide charging current for the parasitic capacitance of a column line (CL), TCFD adaptively generates the required charging current by taking advantage of the parasitic capacitance of another adjacent CL. The TCFD can dramatically enhance the data driving speed by driving a CL with the summing current of data and the required charging current. The adaptive generation of the required charging current and the summing operation are realized by the simultaneous operation of negative- and positive-feedback loops. The loop transfer function is revealed and the stability conditions are discussed. By applying the TCFD, a 7 ??s driving speed is achieved for 20 nA of data current. The driving speeds are almost constant for CL conditions up to 6 k?? and 40 pF. The TCFD is fabricated in a standard 0.35-??m CMOS process and the performance of the TCFD is evaluated by on-chip panel emulation. View full abstract»

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  • Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL

    Publication Year: 2010 , Page(s): 548 - 555
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (847 KB) |  | HTML iconHTML  

    This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock. The clock rate of the digital filter is scaled down by eight from the 3.5-GHz input to allow its implementation with standard cells. The occurrence of a limit cycle is analytically predicted and properly minimized, and its effect on the PLL phase noise is discussed. The circuit fabricated in 90-nm CMOS entails 16 delay stages, which lock to the input frequency in the 2.9-3.9-GHz range (limited by the available signal source). The delay of each TDC cell can be controlled with 50-fs step and the TDC time resolution is 16 ps at 3.9 GHz. The power consumption ranges between 8.1 and 16.5 mW, respectively. The limit-cycle-induced spur is below - 50 dBc. The area occupation is 0.032 mm2. View full abstract»

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  • Calibration and Characterization of Self-Powered Floating-Gate Usage Monitor With Single Electron per Second Operational Limit

    Publication Year: 2010 , Page(s): 556 - 567
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1394 KB) |  | HTML iconHTML  

    Self-powered monitoring refers to a signal processing technique where the computational power is harvested directly from the signal being monitored. In this paper, we present the design and calibration of a CMOS event counter for long-term, self-powered mechanical usage monitoring. The counter exploits a log-linear response of the hot-electron injection process on a floating-gate transistor when biased in weak-inversion. By configuring an array of floating-gate injectors to respond to different amplitude levels of the input signal, a complete analog processor has been designed that implements a level counting algorithm, which is widely used in mechanical usage monitoring. Measured results from a fabricated prototype in a 0.5-??m CMOS process demonstrate that the processor can sense, store and compute over 105 usage cycles with an injection limit approaching one single electron per second and with a counting resolution of 5 bits. This paper also presents a calibration algorithm that is used for compensating the variations which arise due to device mismatch, power supply and temperature fluctuations. The maximum current rating of the fabricated analog processor has been measured to be less than 160 nA making it ideal for practical self-powered sensing applications. View full abstract»

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  • Design of Power-Efficient Configurable Booth Multiplier

    Publication Year: 2010 , Page(s): 568 - 580
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (937 KB) |  | HTML iconHTML  

    In this paper, a power-efficient 16times 16 configurable Booth multiplier (CBM) that supports single 16-b, single 8-b, or twin parallel 8-b multiplication operations is proposed. To efficiently reduce power consumption, a novel dynamic-range detector is developed to dynamically detect the effective dynamic ranges of two input operands. The detection result is used to not only pick the operand with smaller dynamic range for Booth encoding to increase the probability of partial products becoming zero but also deactivate the redundant switching activities in ineffective ranges as much as possible. Moreover, the output product of the proposed multiplier can be truncated to further decrease power consumption by sacrificing a bit of output precision. To efficiently and correctly combine these techniques, some additional components, including a correcting-vector generator, an adjustor, a sign-bit generator, a modified error compensation circuit, etc., are also developed. Finally, three real-life applications are adopted to evaluate the power efficiency and error performance of the proposed multiplier. The results show that the proposed multiplier is more complex than non-CBMs, but significant power and energy savings can be achieved. Furthermore, the proposed multiplier maintains an acceptable output quality for these applications when truncation is performed. View full abstract»

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  • High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

    Publication Year: 2010 , Page(s): 581 - 591
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (526 KB) |  | HTML iconHTML  

    Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource. View full abstract»

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  • New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter

    Publication Year: 2010 , Page(s): 592 - 603
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1329 KB) |  | HTML iconHTML  

    Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementation of finite impulse response (FIR) filter where the filter outputs are computed as inner-product of input-sample vectors and filter-coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same memory and the same number of adders, and less number of input register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR filter is found to involve nearly half the memory-space and (1/N) times the complexity of decoders and input-registers, at the cost of marginal increase in the width of the adders, and additional \sim(4N\times W) AND-OR-INVERT gates and \sim(2N\times W) NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves ne- - arly 15% less area than the DA-based design for the same throughput and lower latency of implementation. View full abstract»

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  • A Min–Max Optimization Framework for Designing \Sigma \Delta Learners: Theory and Hardware

    Publication Year: 2010 , Page(s): 604 - 617
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1466 KB) |  | HTML iconHTML  

    In this paper, we present a framework for constructing ΣΔ learning algorithms and hardware that can identify and track low-dimensional manifolds embedded in a high-dimensional analog signal space. At the core of the proposed approach is a min-max stochastic optimization of a regularized cost function that combines machine learning with ΣΔ modulation. As a result, the algorithm not only produces a quantized sequence of the transformed analog signals but also a quantized representation of the transform itself. The framework is generic and can be extended to higher order ΣΔ modulators and for different signal transformations. In this paper, the ΣΔ learning is demonstrated for identifying linear compression manifolds, which can eliminate redundant AD conversion (ADC) paths. This improves the energy efficiency of the proposed architecture compared to a conventional multichannel data acquisition system. Measured results from a four channel prototype fabricated in a 0.5 μm CMOS process has been used to verify the energy efficiency of the ΣΔ learner and to demonstrate its real-time adaptation capabilities that are consistent with the theoretical and simulated results. One of the salient features of ΣΔ learning is its self-calibration property, whereby the performance remains unchanged even in the presence of computational artifacts (mismatch and nonlinearities). This property makes the proposed architecture ideal for implementing practical high-dimensional AD converters. View full abstract»

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  • Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances

    Publication Year: 2010 , Page(s): 618 - 630
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1394 KB) |  | HTML iconHTML  

    The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (????M) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 ??m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ????Ms characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ????M characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ????M design flow. View full abstract»

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  • Observer-Controller Digital PLL

    Publication Year: 2010 , Page(s): 631 - 641
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (762 KB) |  | HTML iconHTML  

    A digital phase-locked loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. By employing a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC), the loop filter of a DPLL becomes all-digital. Instead of designing the loop filter by digitizing a continuous-time loop response as has been commonly done, more sophisticated control schemes can be employed. In this paper, we propose to design the feedback loop in the time-domain by first modeling the DCO and TDC as a noisy ??plant?? in state-space form. Based on a Kalman observer of the ??plant,?? the proposed approach then generates optimal control signals that accurately account for the additive noise as well as the transport delay in the digital feedback system. The proposed observer-controller loop filter achieves rapid transient response time and significantly reduces the steady-state phase noise jitter compared to the conventional DPLL. Furthermore, the proposed approach enables modeling of other noise sources such as due to oscillator pulling, which is a common problem in many modern transceivers. By employing the observer-controller loop filter, the effect of oscillator pulling can be effectively removed without degrading the overall phase noise performance. View full abstract»

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  • The Spectrum of a Noisy Free-Running Oscillator Explained by Random Frequency Pulling

    Publication Year: 2010 , Page(s): 642 - 653
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    We show that the Lorentzian spectrum of a free-running LC oscillator arises from the random pulling of its frequency by circuit noise sources. To prove this, we analyze the oscillator's spectrum using Adler's differential equation, first in response to pulling by a single injected tone and then by two tones mirrored around the free-run frequency. A novel analysis predicts the frequencies and amplitudes of the sidebands caused by the phase modulation that results. Ultimately, we show that frequency pulling by white noise accounts for the Lorentzian broadening of the oscillator spectrum, and that a complete pulling analysis predicts the same linewidth as a simple circuit analysis. View full abstract»

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  • Synchronization Analysis of Two Weakly Coupled Oscillators Through a PPV Macromodel

    Publication Year: 2010 , Page(s): 654 - 663
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (539 KB) |  | HTML iconHTML  

    This paper adopts a phase-domain macromodel based on perturbation projection vector to study the synchronization effects that take place between two weakly coupled oscillators. Original closed-form expressions for the locking region of the coupled oscillators and for the common locking frequency are derived. The route to synchronization is described analytically by predicting the oscillation frequency shifts, which are induced by mutual pulling as a function of the interaction strength. Under the assumption of a weak coupling, the proposed approach can be applied to a wide class of oscillator topologies. View full abstract»

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  • Noisy Component Extraction (NoiCE)

    Publication Year: 2010 , Page(s): 664 - 671
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1265 KB) |  | HTML iconHTML  

    To achieve efficient blind source extraction (BSE) from noisy mixtures, we propose a noisy component extraction (NoiCE) algorithm that combines standard BSE and a cascaded nonlinear adaptive estimator. There are no assumptions of statistical independence, and also as a byproduct of BSE after deflation, we may also obtain asymptotic identification of the a prioriunknown observation noise sources. By yielding an asymptotically efficient estimator in the presence of an unknown observation noise, the proposed algorithm may also be viewed as a robust approach to NoiCE. Simulations on both synthetic and real-world data confirm the validity of the proposed algorithm in noisy mixing environments. View full abstract»

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  • On Pinning Synchronization of Directed and Undirected Complex Dynamical Networks

    Publication Year: 2010 , Page(s): 672 - 680
    Cited by:  Papers (54)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB) |  | HTML iconHTML  

    This paper presents some low-dimensional pinning criteria for global synchronization of both directed and undirected complex networks, and proposes specifically pinning schemes to select pinned nodes by investigating the relationship among pinning synchronization, network topology, and the coupling strength. The paper answers the challenging questions in pinning control of complex networks: 1) what sufficient conditions can guarantee global asymptotic stability of the pinning process; 2) what nodes should be chosen as pinned candidates; and 3) how many nodes are needed to be pinned for a fixed coupling strength? Furthermore, an adaptive pinning control scheme is developed to achieve synchronization of general complex networks. Numerical examples are given to verify our theoretical analysis. View full abstract»

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  • Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications

    Publication Year: 2010 , Page(s): 681 - 690
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1584 KB) |  | HTML iconHTML  

    The high complexity and time-varying workload of emerging multimedia applications poses a major challenge for dynamic voltage scaling (DVS) algorithms. Although many DVS algorithms have been proposed for real-time applications, an efficient method for evaluating the optimality of such DVS algorithms for multimedia applications does not yet exist. In this paper, we propose the first offline linear programming (LP) method to determine the minimum energy consumption for processing multimedia tasks under stringent delay deadlines. On the basis of the obtained energy lower bound, we evaluate the optimality of various existing DVS algorithms. Furthermore, we extend the LP formulation in order to construct an online DVS algorithm for real-time multimedia processing based on robust sequential linear programming. Simulation results obtained by decoding a wide range of video sequences show that, on average, our online algorithm provides a scheduling solution that requires less than 0.3% more energy than the optimal lower bound with only 0.03% miss rate. In comparison, a very recent algorithm consumes approximately 4% more energy than the optimal lower bound at the same miss rate. View full abstract»

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  • Robust Adaptive Control of a Class of Nonlinear Systems and Its Applications

    Publication Year: 2010 , Page(s): 691 - 702
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (590 KB) |  | HTML iconHTML  

    This paper addresses a global robust adaptive control problem for a class of uncertain nonlinear systems by output feedback control. The problem will be solved by the internal model design method. As our problem formulation includes the chaotic control and synchronization problem of some typical nonlinear systems as special cases, a direct application of our main result will lead to the solution of some interesting control problems such as the global disturbance rejection of the FitzHugh–Nagumo system and the robust output synchronization of the generalized Lorenz system and the harmonic system. View full abstract»

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  • Semi-Blind Most Significant Tap Detection for Sparse Channel Estimation of OFDM Systems

    Publication Year: 2010 , Page(s): 703 - 713
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (539 KB) |  | HTML iconHTML  

    In this paper, a very efficient semi-blind approach for the detection of most significant taps (MSTs) in sparse orthogonal frequency-division multiplexing (OFDM) channel estimation is developed. The least square (LS) estimation problem of sparse OFDM channels is first formulated, showing that the key to sparse channel estimation lies in the detection of the MSTs. An in-depth study of the second-order statistics of the signal received through a noise-free sparse OFDM channel reveals the sparsity and other properties of the correlation functions of the received signal. These properties lead to a direct relationship between the positions of the MSTs of the sparse channel and the most significant lags of the correlation functions, which is then used in conjunction with a pilot-assisted LS estimation to detect the MSTs in a semi-blind fashion. It os also shown that the new MST detection algorithm can be extended for the estimation of multiple-input–multiple-output (MIMO)–OFDM channels. A number of computer-simulation-based experiments for various sparse channels are carried out to confirm the effectiveness of the proposed semi-blind approach. View full abstract»

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  • Wireless Voltage Regulation for Passive Transponders Using an IF to Communicate

    Publication Year: 2010 , Page(s): 714 - 724
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1768 KB) |  | HTML iconHTML  

    This paper presents a novel architecture for wireless communication systems made up of a base station and a remotely powered transponder. The architecture enables the base station to perform wireless voltage regulation (WVR) of the rectifier's output voltage in the transponder. This new regulation technique can be embedded in any system, provided that the passive transponder uses an IF to transmit data to the base station. The technique relies on a large scale, wireless feedback loop that includes the base station, and the transponder. The overall power efficiency of the system is improved compared to conventional voltage regulation technique. A small-signal model is derived to gain some insight on the dynamics and on the stability of the feedback loop. Measurements were made on an actual system operating in far field at 866.6 MHz. They demonstrate the efficiency improvement related to the use of WVR. The validity of the small-signal model is discussed according to the measurement results. View full abstract»

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  • Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers

    Publication Year: 2010 , Page(s): 725 - 734
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1515 KB) |  | HTML iconHTML  

    A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It is based on the analysis of the operation and power loss mechanism of class-E PAs, which includes the effects of a finite dc-feed inductance and an impedance matching transformer. Using the proposed approach, a class-E PA with a 2 \times 1:2 step-up on-chip transformer was implemented in a 0.18- \mu{\hbox {m}} CMOS technology. With a 3.3 V supply, the fully integrated PA achieves an output power of 2 W and a power-added efficiency of 31% at 1.8 GHz. View full abstract»

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  • icecs2010

    Publication Year: 2010 , Page(s): 735
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  • [Call for papers - biocas2010]

    Publication Year: 2010 , Page(s): 736
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2010 , Page(s): C3
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras