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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 2 • Date Feb. 2010

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2010 , Page(s): C2
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  • Tree-Structured DEM DACs with Arbitrary Numbers of Levels

    Publication Year: 2010 , Page(s): 313 - 322
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (473 KB) |  | HTML iconHTML  

    Unity-weighted tree-structured dynamic element matching (DEM) DACs are widely used in delta-sigma (????) data converters to ensure that mismatches among nominally identical analog components give rise to shaped noise instead of nonlinear distortion. Tree-structured DEM DACs offer an advantage over other published DEM DACs in that the shaped noise from component mismatches can be made free of spurious tones. However, previously published unity-weighted tree-structured DEM DACs have the disadvantage that they require a power-of-two number of nominally identical 1-bit DACs. When applied to a ???? data converter with a non-power-of-two number of quantization steps, this requires the DEM DAC to have a larger input range than needed by the ???? data converter which wastes power and circuit area. This paper presents a generalized tree-structured DEM encoder applicable to DEM DACs with any number of 1-bit DACs, thereby avoiding this limitation. View full abstract»

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  • EMI-Resistant CMOS Differential Input Stages

    Publication Year: 2010 , Page(s): 323 - 331
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB) |  | HTML iconHTML  

    This paper studies and compares the performances of CMOS differential input stages with a high degree of immunity against electromagnetic interferences (EMIs) and introduces a source-buffered differential pair which is very resistant to EMI coupled at its inputs. The EMI behavior of this source-buffered differential-pair topology has been evaluated with a test chip: When injecting an EMI signal of 750 mV rms at the input terminals, the measured maximal EMI-induced input offset voltage corresponds to 116 mV for the source-buffered topology compared with 610 mV for the classic differential pair, which constitutes a major improvement. View full abstract»

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  • Noise in Current-Commutating Passive FET Mixers

    Publication Year: 2010 , Page(s): 332 - 344
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1238 KB) |  | HTML iconHTML  

    Noise in the mixer of zero-IF receivers can compromise the overall receiver sensitivity. The evolution of a passive CMOS mixer based on the knowledge of the physical mechanisms of noise in an active mixer is explained. Qualitative physical models that simply explain the frequency translation of both the flicker and white noise of different FETs in the mixer have been developed. Derived equations have been verified by simulations, and mixer optimization has been explained. View full abstract»

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  • Analysis of Adaptive Digital Feedback Linearization Techniques

    Publication Year: 2010 , Page(s): 345 - 354
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    A new lookup-table linearization technique is developed based on the digital feedback and digital feedback/predistortion (DFBPD) concepts. The linearization characteristics are investigated through system simulation of a real power-amplifier model with 90-W peak envelope power. The DFB suppresses forward-path nonlinear distortion as a gain reduction due to the FB effect, and this technique enhances the system tolerance without any bandwidth limitation. As the PD network is added to the FB loop, the linearization performance and system tolerance are further improved because of more accurate PD signal extraction. In addition, the gain is purely determined by the FB path, so the gain fluctuation in the forward path, including amplifier aging and temperature effects, is suppressed. The analysis and simulation allow experimental evaluation of the linearization mechanism and performance of the DFBPD technique for an 802.16 e mobile Worldwide Interoperability for microwave access signal. View full abstract»

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  • Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits

    Publication Year: 2010 , Page(s): 355 - 367
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (863 KB) |  | HTML iconHTML  

    In this paper, a novel class of power analysis attacks to cryptographic circuits is presented. These attacks aim at recovering the secret key of a cryptographic core from measurements of its static (leakage) power. These attacks exploit the dependence of the leakage current of CMOS integrated circuits on their inputs (including the secret key of the cryptographic algorithm that they implement), as opposite to traditional power analysis attacks that are focused on the dynamic power. For this reason, this novel class of attacks is named ??leakage power analysis?? (LPA). Since the leakage power increases much faster than the dynamic power at each new technology generation, LPA attacks are a serious threat to the information security of cryptographic circuits in sub-100-nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks that is based on a solid theoretical background is presented. Advantages and measurement issues are also analyzed in comparison with traditional power analysis attacks based on dynamic power measurements. Examples are provided for various circuits, and an experimental attack to a register is performed for the first time. An analytical model of the LPA attack result is also provided to better understand the effectiveness of this technique. The impact of technology scaling is explicitly addressed by means of a simple analytical model and Monte Carlo simulations. Simulations on a 65- and 90-nm technology and experimental results are presented to justify the assumptions and validate the leakage power models that are adopted. View full abstract»

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  • A New Criterion for the Design of Variable Fractional-Delay FIR Digital Filters

    Publication Year: 2010 , Page(s): 368 - 377
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (870 KB) |  | HTML iconHTML  

    Conventionally, variable fractional-delay finite-impulse-response digital filters are generally designed by minimizing the root-mean-square error of variable frequency response. In this paper, a new criterion concerning the minimization of the root-mean-square error of variable group-delay response is proposed. However, minimization is a highly nonlinear problem, so an iterative method is proposed in this paper to overcome it. To further reduce the maximum absolute group-delay error in the least squares design, an iterative weighting-updated technique is also proposed, which constitutes the outer loop of the overall iterative process while the iteration stated earlier makes up the inner loop. Several design examples will be presented to demonstrate the effectiveness of the proposed method. View full abstract»

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  • Minimax Design of IIR Digital Filters Using SDP Relaxation Technique

    Publication Year: 2010 , Page(s): 378 - 390
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    This paper presents a new algorithm using semidefinite programming (SDP) relaxation to design infinite impulse response digital filters in the minimax sense. Unlike traditional design algorithms that try to directly minimize the error limit, the proposed algorithm employs a bisection searching procedure to locate the minimum error limit of the approximation error. Given a fixed error limit at each iteration, the SDP relaxation technique is adopted to formulate the design problem in a convex form. In practice, the true minimax design cannot be always obtained. Thus, a regularized feasibility problem is adopted in the bisection searching procedure. The stability of the designed filters can also be guaranteed by adjusting the regularization coefficient. Unlike other sequential design methods, the proposed algorithm tries to find a feasible solution at each iteration of the sequential design procedure within a feasible set defined by the relaxed constraints. This feasible set is not restricted within the neighborhood of a given point obtained from the previous iteration. Thus, the proposed method can avoid being trapped in the locally minimum point. Four examples are presented in this paper to demonstrate the effectiveness of the proposed method. View full abstract»

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  • Design of Fractional Delay Filter, Differintegrator, Fractional Hilbert Transformer, and Differentiator in Time Domain With Peano Kernel

    Publication Year: 2010 , Page(s): 391 - 404
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2997 KB) |  | HTML iconHTML  

    In this paper, we propose a fractional delay filter, an integer-order differintegrator, a fractional Hilbert transformer, and a fractional differintegrator. Through the time-domain analysis on the desired input and output signals of a linear time-invariant system, we derive a set of linear equations, which can be solved to obtain the coefficients of the desired filter. We also show that the difference between the desired output signal and the actual output of the system can be represented as the convolution of the derivative of the input signal and the Peano kernel. View full abstract»

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  • Analysis of Slow-Scale Instability in Boost PFC Converter Using the Method of Harmonic Balance and Floquet Theory

    Publication Year: 2010 , Page(s): 405 - 414
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1174 KB) |  | HTML iconHTML  

    In this paper, the slow-scale instability in a boost PFC converter under average current mode control is studied via the harmonic balance method and floquet theory. Systematic and general numerical algorithm of the technique is developed. The objective is to identify instability of the system. If instability exists, the type of bifurcation and the boundaries of slow-scale instability in the parameter space of the system can be found for facilitating the design of such converters. Firstly, based on the fact that the current compensator is designed very well and what we considered is the slow-scale instability, the simplified model of a boost PFC converter under average current mode control is derived. And then, the solution of the simplified model is calculated by using the harmonic balance method. Subsequently, both the stability of the circuit system and the type of bifurcation are identified via floquet theory. Meanwhile, the critical conditions of the stable operation in the parameter space of the system are given accurately. Finally, experimental results are presented for the verification of the analytical results. View full abstract»

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  • Dynamics and Stability Issues of a Single-Inductor Dual-Switching DC–DC Converter

    Publication Year: 2010 , Page(s): 415 - 426
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1710 KB) |  | HTML iconHTML  

    A single-inductor two-input two-output power electronic dc-dc converter can be used to regulate two generally nonsymmetric positive and negative outputs by means of a pulsewidth modulation with a double voltage feedback. This paper studies the dynamic behavior of this system. First, the operation modes and the steady-state properties of the converter are addressed, and, then, a stability analysis that includes both the power stage and control parameters is carried out. Different bifurcations are determined from the averaged model and from the discrete-time model. The Routh-Hurwitz criterion is used to obtain the stability regions of the averaged (slow-scale) dynamics in the design parameter space, and a discrete-time approach is used to obtain more accurate results and to detect possible (fast-scale) subharmonic oscillations. Experimental measurements were taken from a system prototype to confirm the analytical results and numerical simulations. Some possible nonsmooth bifurcations due to the change in the switching patterns are also illustrated. View full abstract»

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  • Improved Small-Signal Analysis for Circuits Working in Periodic Steady State

    Publication Year: 2010 , Page(s): 427 - 437
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1303 KB) |  | HTML iconHTML  

    This paper considers the formulation of the variational model (VM) of autonomous circuits (oscillators) working in periodic steady-state conditions. The shooting method, which is largely used to compute the solution in the time domain when the VM is forced by a small-signal perturbation, is studied. The proposed analytical approach can be exploited to improve accuracy in the simulation of the effects of noise sources. In particular, we justify from an analytical standpoint the adoption of a suitable periodicity constraint in the shooting method. We exploit the properties of block circulant matrices that naturally arise in the description of the problem. We prove that the frequency of the small-signal perturbation must be different from that of the unperturbed oscillator to avoid inaccuracy of the shooting method due to the existence of singularities in the VM formulation, and derive a method that allows us to get closer to the singularity. View full abstract»

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  • Algebraic Approach to Ambiguity-Group Determination in Nonlinear Analog Circuits

    Publication Year: 2010 , Page(s): 438 - 447
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB) |  | HTML iconHTML  

    In this paper, a symbolic procedure for ambiguity-group determination, based on the a priori identifiability concept, is proposed. The method starts from the analysis of the occurrence of circuit parameters in the coefficients of the input/output relationship in order to select the potential canonical ambiguity groups. This first step allows one to strongly reduce the problem complexity. In a second step, the obtained nonlinear system that imposes the ambiguity conditions is solved, resorting to Gro??bner bases theory. Both of these steps are completely symbolic, thus avoiding round-off errors. Furthermore, the method can be applied to both linear and nonlinear circuits. An alternative approach is also proposed, which extends to nonlinear circuits a method presented in the literature, which can be directly applied only to linear circuits. The methods are illustrated by means of benchmarks regarding well-known linear and nonlinear circuits. View full abstract»

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  • Improving the Performance of Chaos-Based Modulations Via Serial Concatenation

    Publication Year: 2010 , Page(s): 448 - 459
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (766 KB) |  | HTML iconHTML  

    This paper proposes a serially concatenated system with an outer convolutional channel encoder and an inner chaos-based coded modulator. With the help of the principles of symbolic dynamics, the chaotic modulation can be described in terms of a trellis. Owing to this, we show that the resulting system can be designed and analyzed following developments made for serially concatenated channel codes (SCCCs) or bit-interleaved coded-modulation systems. We show how the iterative decoding algorithm used in this concatenated framework can be analyzed through the well-known extrinsic information transfer chart device and how the bit error rate can be bounded using the transfer function of the convolutional channel encoder. Comparison with a related SCCC system in both additive white Gaussian noise and frequency-nonselective fading channels shows that this kind of chaos-based systems keeps the potential advantages of coded-modulation-based systems. We are thus confident that the principles shown here can lead to the design of competitive chaotic discrete communication systems. View full abstract»

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  • A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems

    Publication Year: 2010 , Page(s): 460 - 470
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3454 KB) |  | HTML iconHTML  

    This paper presents an in-car networking transceiver front end that is compliant with FlexRay automotive electronic standards. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. In order to resist process and temperature variation, a 20-MHz clock generator with process, supply voltage, and temperature compensation is proposed in this paper. A prototype system as well as a chip implemented by using a typical 0.18 ??m single-poly six-metal CMOS process is reported in this paper. The proposed prototypical transceiver front end has been tested by the thermo chamber and a FlexRay development board to certify its operation in the [-40??C-+125??C] temperature range and FlexRay standards. The power consumption of the whole chip is 43.01 mW at a 10 Mbit/s throughput. The core area of this design is 0.117 mm2. The maximal throughput of the proposed prototypical transceiver front end can reach 40 Mbit/s. View full abstract»

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  • Development of the Area-Reducing Active “Coil-Enhancement” Principle, Practiced Onto an ADSL–POTS Splitter

    Publication Year: 2010 , Page(s): 471 - 480
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1140 KB) |  | HTML iconHTML  

    This paper describes the theory behind the "coil-enhancement" principle: The impedance of an inductor is made controllable as a function of the frequency by means of a transconductance function g m (s) that is located in the feedback loop. In order to show the potential of the coil-enhancement circuit, the effect of several basic transconductance functions onto the synthesized impedance is presented. The specific case of g m (s) ˜ s -1 produces the coil-enhancement situation and is discussed in detail. One drawback of the coil-enhancement circuit is found in the series resistance of a second inductor, also positioned in the feedback loop. The influence of this series resistance onto the synthesized impedance is addressed and a work-around is presented. A newly developed active "plain old telephone service" (POTS) splitter, based upon the coil-enhancement principle, is derived from a fully passive POTS splitter in which two large inductors are merged together into one active inductor. The active POTS splitter is fully tested and is found compliant with the standard "TS 101 952-1-1 V1.2.1 (option A)" of the European Telecommunications Standards Institute. The area reduction that comes together with the passive-to-active conversion is 40%. View full abstract»

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  • A Discrete-Time Digital-IF Interference-Robust Ultrawideband Pulse Radio Transceiver Architecture

    Publication Year: 2010 , Page(s): 481 - 494
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1014 KB) |  | HTML iconHTML  

    This paper discusses the challenges in ultrawideband pulse radio transceiver design and proposes an architecture operating between 3.1 and 10.6 GHz to address them. The 7.5-GHz band is subdivided into multiple channels of 500 MHz each to relax the requirements for pulse generation, transceiver synchronization, and group-delay flatness. The pulse bases for these channels are stored in digital memories and are used for pulse generation on the transmit side and correlation on the receive side. The transceiver can operate in combination with a fast interferer detector that quickly sweeps through the channels to determine which channels are occupied by large interferers and are thus unsuitable for communication. The all-digital pulse bases allow the transceiver to quickly switch between different channels to avoid interferers without needing multiple or, alternatively, broadband fast-settling phase-locked loops. The frequency plan allows the most critical 802.11 interferers to be pushed to higher frequencies during the first block downconversion where they are attenuated by the low-pass filters of the receiver. The wideband intermediate-frequency correlation architecture significantly relaxes the speed requirement of the digital circuit and the local memories. Several signal-processing techniques to eliminate sampling images in the transmitter as well as spurious image responses in the receiver are also presented. The proposed architecture is digitally intensive and, hence, can take advantage of technology scaling. View full abstract»

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  • Adaptive Impedance-Matching Techniques for Controlling L Networks

    Publication Year: 2010 , Page(s): 495 - 505
    Cited by:  Papers (14)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1138 KB) |  | HTML iconHTML  

    The link quality of mobile phones suffers from antenna mismatch due to fluctuating body effects. Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch. To secure reliable convergence, a cascade of two control loops is proposed for independent control of the real and imaginary parts of impedance. A secondary feedback path is used to enforce operation into a stable region when needed. These techniques exploit the basic properties of tunable series and parallel LC networks. A generic quadrature detector that offers a power-independent orthogonal reading of the complex impedance value is presented, which is used for direct control of variable capacitors. This approach renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna-matching modules. View full abstract»

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  • A Li-Ion Battery Charger With Smooth Control Circuit and Built-In Resistance Compensator for Achieving Stable and Fast Charging

    Publication Year: 2010 , Page(s): 506 - 517
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2775 KB) |  | HTML iconHTML  

    A built-in resistance compensator (BRC) technique is presented to speed up the charging time of a lithium-ion battery. A smooth control circuit (SCC) is proposed to ensure the stable transition from the constant-current (CC) to the constant-voltage (CV) stage. Due to the external parasitic resistance of the Li-ion battery-pack system, the charger circuit switches from the CC to the CV stage without fully charging the cell. The BRC technique dynamically estimates the external resistance to extend the CC stage. The experimental results show that the period of the CC stage can be extended to 40% of that of the original design. The charging time is effectively reduced. View full abstract»

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  • IMD of Closed-Loop Filterless Class D Amplifiers

    Publication Year: 2010 , Page(s): 518 - 527
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    Audio amplifiers, including the contemporary class D amplifiers (CDAs), are typically qualified by their several nonlinearities, including total harmonic distortion and intermodulation distortion (IMD). In the case of filterless CDAs, IMD remains largely unexplored, and the mechanism thereof is largely unknown. This paper presents an analytical modeling of IMD for the prevalent first- and second-order filterless CDAs and shows that the dominant mechanisms of the former is phase error while of the latter is duty-cycle error. By means of multidimensional Fourier series analysis, analytical expressions for the IMD components and thereafter, the IMD expression for these CDAs, are derived. The derived expressions depict that the IMDs of these CDAs are significant, and the IMD of the first-order filterless CDA, in spite of its lower noise-suppression attribute, is somewhat unexpectedly superior to the second-order filterless CDA. Furthermore, the derived expressions delineate the parameters that affect IMD and are insightful to designers to optimize/vary pertinent parameters to reduce IMD. The derived IMD expressions are verified against HSPICE simulations and on the basis of measurements on a prototype CDA IC and other CDAs realized discretely. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2010 , Page(s): 528
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2010 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras