IBM Journal of Research and Development

Volume 34 Issue 1 • Jan. 1990

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Displaying Results 1 - 15 of 15
  • Preface

    Publication Year: 1990, Page(s):2 - 3
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | PDF file iconPDF (102 KB)
    Freely Available from IEEE
  • The evolution of RISC technology at IBM

    Publication Year: 1990, Page(s):4 - 11
    Cited by:  Papers (3)  |  Patents (15)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (331 KB)

    This paper traces the evolution of IBM RISC architecture from its origins in the 1970s at the IBM Thomas J. Watson Research Center to the present-day IBM RISC System/6000* computer. The acronym RISC, for Reduced Instruction-Set Computer, is used in this paper to describe the 801 and subsequent architectures. However, RISC in this context does not strictly imply a reduced number of instructions, bu... View full abstract»

    Freely Available from IEEE
  • The IBM RISC System/6000 processor: Hardware overview

    Publication Year: 1990, Page(s):12 - 22
    Cited by:  Papers (21)  |  Patents (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (531 KB)

    A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System/6000* family is based on the new IBM POWER (Performance Optimization With Enhanced RISC) architecture; the hardware implementation takes advantage of this powerful RISC architecture and employs sophisticated design techniques to achieve a short cycle time and a low cycles-per-ins... View full abstract»

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  • IBM RISC System/6000 processor architecture

    Publication Year: 1990, Page(s):23 - 36
    Cited by:  Papers (24)  |  Patents (29)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (646 KB)

    This paper describes the hardware architecture of the IBM RISC System/6000* processor, which combines basic RISC principles with a partitioning of registers by function into multiple ALUs. This allows a high degree of parallelism in execution and permits a compiler to generate highly optimized code to manage the interaction among parallel functions. Floating-point arithmetic is integrated into the... View full abstract»

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  • Machine organization of the IBM RISC System/6000 processor

    Publication Year: 1990, Page(s):37 - 58
    Cited by:  Papers (60)  |  Patents (29)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1004 KB)

    The IBM RISC System/6000* processor is a second-generation RISC processor which reduces the execution pipeline penalties caused by branch instructions and also provides high floating-point performance. It employs multiple functional units which operate concurrently to maximize the instruction execution rate. By employing these advanced machine-organization techniques, it can execute up to four ins... View full abstract»

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  • Design of the IBM RISC System/6000 floating-point execution unit

    Publication Year: 1990, Page(s):59 - 70
    Cited by:  Papers (88)  |  Patents (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (819 KB)

    The IBM RISC System/6000* (RS/6000) floating-point unit (FPU) exemplifies a second-generation RISC CPU architecture and an implementation which greatly increases floating-point performance and accuracy. The key feature of the FPU is a unified floating-point multiply-add-fused unit (MAF) which performs the accumulate operation (A times B) + C as an indivisible operation. This single functional unit... View full abstract»

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  • Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit

    Publication Year: 1990, Page(s):71 - 77
    Cited by:  Papers (40)  |  Patents (40)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (401 KB)

    This paper presents a novel technique used in the multiply-add-fused (MAF) unit of the IBM RISC System/6000* (RS/6000) processor for normalizing the floating-point results. Unlike the conventional procedures applied thus far, the so-called leading-zero anticipator (LZA) of the RS/6000 carries out processing of the leading zeros and ones in parallel with floating-point addition. Therefore, the new ... View full abstract»

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  • Pseudorandom built-in self-test methodology and implementation for the IBM RISC System/6000 processor

    Publication Year: 1990, Page(s):78 - 84
    Cited by:  Papers (21)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (414 KB)

    This paper describes a unified self-test and system bring-up methodology. The components involved include a common on-chip processor (COP) that executes the chip self-test sequence and provides an interface to the COP bus, a serial bus (COP bus) that links the chips to OCS and ESP, an on-card sequencer (OCS) that controls the self-test and system initialization sequences, and an engineering suppor... View full abstract»

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  • Instruction scheduling for the IBM RISC System/6000 processor

    Publication Year: 1990, Page(s):85 - 92
    Cited by:  Papers (20)  |  Patents (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (352 KB)

    For fast execution on the IBM RISC System/6000* processor, instructions should be arranged in an order that uses the arithmetic units as efficiently as possible. This paper describes the scheduling requirements of the machine, and a scheduling algorithm for it that is used in two compilers. View full abstract»

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  • Instruction scheduling beyond basic blocks

    Publication Year: 1990, Page(s):93 - 97
    Cited by:  Papers (9)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (290 KB)

    Instruction scheduling consists of the rearrangement or transformation of program statements, usually at the intermediate language or assembly code level, in order to reduce possible run-time delays between instructions. Such transformations must preserve data dependency and are subject to other constraints. Highly optimizing compilers employing instruction-scheduling techniques have proven to be ... View full abstract»

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  • Managing programs and libraries in AIX Version 3 for RISC System/6000 processors

    Publication Year: 1990, Page(s):98 - 104
    Cited by:  Papers (1)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (288 KB)

    This paper describes the program and program-library management facility that has been developed for the AIX* operating system, Version 3, as implemented for the IBM POWER (Performance Optimization With Enhanced RISC) architecture. It provides run-time loading of libraries, symbol resolution with type checking, and relocation. In addition, the use of the loader to add programs to an already runnin... View full abstract»

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  • Evolution of storage facilities in AIX Version 3 for RISC System/6000 processors

    Publication Year: 1990, Page(s):105 - 110
    Cited by:  Papers (6)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (285 KB)

    The AIX* Version 3 storage facilities include features not found in other implementations of the UNIX†operating system. Maximum virtual memory is more than 1000 terabytes and is used pervasively to access all files and the meta-data of the file systems. Each separate file system (subtree) of the file name hierarchy occupies a logical disk volume, composed of space from possibly several ... View full abstract»

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  • Computation of elementary functions on the IBM RISC System/6000 processor

    Publication Year: 1990, Page(s):111 - 119
    Cited by:  Papers (51)  |  Patents (42)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (425 KB)

    The additional speed and precision of the IBM RISC System/6000* floating-point unit have motivated reexamination of algorithms to perform division, square root, and the elementary functions. New results are obtained which avoid the necessity of doing special testing to get the last bit rounded correctly in accordance with all of the IEEE rounding modes in the case of division and square root. For ... View full abstract»

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  • Recent publications by IBM authors

    Publication Year: 1990, Page(s):120 - 130
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (491 KB)

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author cited. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Publication Year: 1990, Page(s):131 - 136
    IEEE is not the copyright holder of this material | PDF file iconPDF (227 KB)
    Freely Available from IEEE

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Editor-in-Chief
Rachel D'Annucci Henriquez
IBM T. J. Watson Research Center