# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2009, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2009, Page(s): C2
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• ### Editorial: A Few Comments Before Leaving the Helm

Publication Year: 2009, Page(s):2529 - 2532
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• ### A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique

Publication Year: 2009, Page(s):2533 - 2543
Cited by:  Papers (12)  |  Patents (2)
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This paper presents a low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique. The comparison of the noise-cancellation ability with the correlated double sampling and chopper-stabilization techniques is demonstrated; also, the noise performance of these cancellation techniques is observed and discussed. Using the proposed technique, the modulator achieves 92 d... View full abstract»

• ### Design Optimization of On-Chip Inductive Peaking Structures for 0.13-$mu{hbox {m}}$ CMOS 40-Gb/s Transmitter Circuits

Publication Year: 2009, Page(s):2544 - 2555
Cited by:  Papers (25)  |  Patents (1)
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This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual... View full abstract»

• ### Second-Order Intermodulation in Current-Commutating Passive FET Mixers

Publication Year: 2009, Page(s):2556 - 2568
Cited by:  Papers (22)  |  Patents (1)
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Amplitude-modulation detection in the mixer plagues the performance of the zero-intermediate-frequency receiver by downconverting the envelope of amplitude modulated blockers to baseband where the desired channel is after downconversion. Simple equations based on physical mechanisms of second-order intermodulation generation have been derived which can predict the IIP2 of the current-driven passiv... View full abstract»

• ### Settling Time Optimization for Three-Stage CMOS Amplifier Topologies

Publication Year: 2009, Page(s):2569 - 2582
Cited by:  Papers (19)
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A new settling-time-oriented design methodology for the most common three-stage operational amplifier (op-amp) schemes reported in the literature is presented in this paper. The proposed approach allows the systematic sizing of the compensation network in order to reach the best closed-loop op-amp settling behavior. To demonstrate the effectiveness of the methodology and the correctness of the ana... View full abstract»

• ### A Biomedical Implantable FES Battery-Powered Micro-Stimulator

Publication Year: 2009, Page(s):2583 - 2596
Cited by:  Papers (8)  |  Patents (2)
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The integrated circuit (IC) designs of an implantable functional electrical stimulation (FES) battery-powered micro-stimulator are presented in this paper. The battery is recharged by receiving power magnetically through a coil under supervision of a power management unit. To limit the heat generation on the stimulator when a large magnetic field is present, an on-chip rectifier is capable of limi... View full abstract»

• ### An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices

Publication Year: 2009, Page(s):2597 - 2608
Cited by:  Papers (7)
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The Gabor transform can be used to represent a signal in terms of a set of pseudo basis functions, allowing a signal to be split into parallel paths of a lower bandwidth. An analog Gabor transform using sub-threshold CMOS continuous time filters designed from time domain impulse responses is described. A novel method for designing low power gm-C filters using simple models of identical transconduc... View full abstract»

• ### Hardware Implementation of ${rm GF}(2^{m})$ LDPC Decoders

Publication Year: 2009, Page(s):2609 - 2620
Cited by:  Papers (53)  |  Patents (5)
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Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation al... View full abstract»

• ### Design of Extrapolated Impulse Response FIR Filters With Residual Compensation in Subexpression Space

Publication Year: 2009, Page(s):2621 - 2633
Cited by:  Papers (8)
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In this paper, an extrapolated impulse response filter with residual compensation is proposed for the design of discrete coefficient finite-impulse response (FIR) filters using subexpression sharing. The proposed technique utilizes the quasi-periodic nature of the filter impulse response to approximate the filter coefficients. The reduced degree of freedom of filter coefficients due to the quasi-p... View full abstract»

• ### A Pipelined FFT Architecture for Real-Valued Signals

Publication Year: 2009, Page(s):2634 - 2643
Cited by:  Papers (52)  |  Patents (1)
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This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm ... View full abstract»

• ### Two-Channel Quincunx QMF Banks Using Two-Dimensional Digital Allpass Filters

Publication Year: 2009, Page(s):2644 - 2654
Cited by:  Papers (2)
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This paper presents a novel structure for the analysis and synthesis filters of two-channel quincunx quadrature mirror filter (QQMF) banks. This structure uses an appropriate combination of 2-D recursive digital allpass filters (DAFs) with symmetric half-plane (SHP) support regions. The proposed analysis/synthesis filters possess a 2-D doubly complementary half-band (DC-HB) property that facilitat... View full abstract»

• ### An Optimization Approach to Single-Bit Quantization

Publication Year: 2009, Page(s):2655 - 2668
Cited by:  Papers (3)  |  Patents (3)
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This paper presents an optimization approach to single-bit quantization. The paper starts by redefining single-bit quantization as a maximum-likelihood sequence detection problem and by showing that the Viterbi algorithm is its optimal solution. It also shows that the conventional ???? converter implements a greedy solution to the same optimization problem. There is, moreover, a continuum of solut... View full abstract»

• ### Closed-Form Analytical Equations for Amplitude and Frequency of High-Frequency CMOS Ring Oscillators

Publication Year: 2009, Page(s):2669 - 2677
Cited by:  Papers (9)
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New closed-form equations are proposed for frequency and amplitude of a ring oscillator. The method is general enough to be used for all types of delay stages. Using exact large-signal circuit analysis, closed-form equations for estimating the frequency and amplitude of a ring oscillator are derived as an example. The method takes into account the effect of various parasitic capacitors to have bet... View full abstract»

• ### Energy Efficiency of Pulsed Actuations on Linear Resonators

Publication Year: 2009, Page(s):2678 - 2688
Cited by:  Papers (3)
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The objective of this paper is to show that under some circumstances, the sign of a sampled sinusoid sequences, briefly S 3, is optimal to provide maximum energy transfer to linear resonators in the context of discrete-time pulsed actuation at periodic times with bounded sequences. It will be proven that there is an optimal S 3 sequence which maximizes the reson... View full abstract»

• ### Global Uniform Synchronization With Estimated Error Under Transmission Channel Noise

Publication Year: 2009, Page(s):2689 - 2702
Cited by:  Papers (8)
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This paper investigates the problem of estimating synchronization errors and its application to global uniform synchronization with an estimated error bound for the master-slave chaos synchronization scheme via linear control input, which is possibly subject to disturbances by unknown but bounded channel noise and time-delay. Based on Lyapunov function, Razumikhin technique, nonlinear parametric v... View full abstract»

• ### Adaptive Observers With Persistency of Excitation for Synchronization of Chaotic Systems

Publication Year: 2009, Page(s):2703 - 2716
Cited by:  Papers (37)
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We address the problem of master-slave synchronization of chaotic systems under parameter uncertainty and with partial measurements. Our approach is based on observer-design theory hence, we view the master dynamics as a system of differential equations with a state and a measurable output and we design an observer (tantamount to the slave system) which reconstructs the dynamic behavior of the mas... View full abstract»

• ### An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Publication Year: 2009, Page(s):2717 - 2727
Cited by:  Papers (7)  |  Patents (1)
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This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unl... View full abstract»

• ### A Calibrated Phase and Amplitude Control System for a 1.9 GHz Phased-Array Transmitter Element

Publication Year: 2009, Page(s):2728 - 2737
Cited by:  Papers (7)  |  Patents (7)
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A system is proposed to allow the phase and amplitude of a signal to be accurately set and regulated over process and power supply variations. It uses a variable gain amplifier (VGA) in conjunction with the phase shifter to compensate for the variable losses of the phase shifter and simultaneously provide a means of adjusting the amplitude of the signal. The system has been fabricated in a 0.18 ??... View full abstract»

• ### A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Publication Year: 2009, Page(s):2738 - 2748
Cited by:  Papers (21)
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A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneousl... View full abstract»

• ### Analysis and Design of an Adaptive-Step-Size Digital Controller for Switching Frequency Autotuning

Publication Year: 2009, Page(s):2749 - 2759
Cited by:  Papers (6)
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An adaptive-step-size autotuning algorithm and controller for power converters' switching frequency optimization with improved convergence performance is presented in this paper. The controller automatically tracks and determines the switching frequency of a power converter in order to achieve the highest power conversion efficiency under variable operating conditions including temperature variati... View full abstract»

• ### ISCAS 2010

Publication Year: 2009, Page(s): 2760
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• ### 2009 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 56

Publication Year: 2009, Page(s):2761 - 2792
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• ### IEEE Circuits and Systems Society Information

Publication Year: 2009, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK