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Signal Processing Magazine, IEEE

Issue 6 • Date November 2009

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Displaying Results 1 - 25 of 34
  • IEEE Signal Processing Magazine - Front cover

    Publication Year: 2009
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  • Table of contents

    Publication Year: 2009
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  • Cross-pollination in signal processing technical areas [From the Editor]

    Publication Year: 2009 , Page(s): 2 - 4
    Cited by:  Papers (3)
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  • What is signal processing? [President's Message]

    Publication Year: 2009 , Page(s): 6
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  • SPS Members Receive IEEE Technical Field Awards [Society News]

    Publication Year: 2009 , Page(s): 8
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  • DSPs are helping to make it hard to get lost [Spotlight Report]

    Publication Year: 2009 , Page(s): 9 - 13
    Cited by:  Papers (2)
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  • Top downloads in IEEE Xplore [Reader's Choice]

    Publication Year: 2009 , Page(s): 14 - 22
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  • How the Hough transform was invented [DSP History]

    Publication Year: 2009 , Page(s): 18 - 22
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    Where did this transform come from? You may vaguely recall learning that it goes back to a 1962 patent by P.V.C. Hough, though the author suspect very few readers have actually looked at that patent, the title page. If you do, you may be surprised to find that the popular transform used today is not described there. Indeed, today's transform was not a single-step invention but instead took several steps that resulted in Hough's initial idea being combined with an idea from an obscure branch of late 19th century mathematics to produce the familiar sinusoidal transform. The previously untold history of how this came about illustrates how important advances sometime come from combining not-obviously-related ideas. The history perhaps also illustrates that the observation of Louis Pasteur, "Chance favors the prepared mind," remains as apt in the 20th and 21st centuries as it was in the 19th. View full abstract»

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  • Signal processing on platforms with multiple cores: Part 1 - Overview and methodologies [From the Guest Editors]

    Publication Year: 2009 , Page(s): 24 - 25
    Cited by:  Papers (3)
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  • A survey of multicore processors

    Publication Year: 2009 , Page(s): 26 - 37
    Cited by:  Papers (39)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1005 KB) |  | HTML iconHTML  

    General-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability has grown. Parallel processing increases performance by adding more parallel resources while maintaining manageable power characteristics. The implementations of multicore processors are numerous and diverse. Designs range from conventional multiprocessor machines to designs that consist of a "sea" of programmable arithmetic logic units (ALUs). In this article, we cover some of the attributes common to all multicore processor implementations and illustrate these attributes with current and future commercial multicore designs. The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals. View full abstract»

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  • Trends in multicore DSP platforms

    Publication Year: 2009 , Page(s): 38 - 49
    Cited by:  Papers (25)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1092 KB) |  | HTML iconHTML  

    In the last two years, the embedded DSP market has been swept up by the general increase in interest in multicore that has been driven by companies such as Intel and Sun. One reason for this is that there is now a lot of focus on tooling in academia and also a willingness on the part of users to accept new programming paradigms. This industry-wide effort will have an effect on the way multicore DSPs are programmed and perhaps architected. But it is too early to say in what way this will occur. Programming multicore DSPs remains very challenging. The problem of how to take a piece of sequential code and optimally partition it across multiple cores remains unsolved. Hence, there will naturally be a lot of variations in the approaches taken. Equally important is the issue of debugging and visibility. Developing effective and easy-to-use code development and real-time debug tools is tremendously important as the opportunity for bugs goes up significantly when one starts to deal with both time and space. The markets that DSP plays in have unique features in their desire for low power, low cost, and hard real-time processing, with an emphasis on mathematical computation. How well the multicore research being performed presently in academia will address these concerns remains to be seen. View full abstract»

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  • Multiprocessor system-on-chip technology

    Publication Year: 2009 , Page(s): 50 - 54
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    Signal processing is a prime application for very large scale integration (VLSI) technology and systems-on-chips (SoCs), so it should be no surprise that a great deal of effort has been put into the design of architectures for signal processing. The need for programmability, real-time performance, and low-power operation are all driving factors in the development of these architectures. Although multicore processors have recently emerged for desktop and server computing, single-chip multiprocessors have a much longer history in embedded computing thanks to the strict requirements placed on these systems. Multiprocessor SoCs (MPSoCs) have been developed in response to the needs of embedded signal processing and multimedia computing. This article surveys the requirements on embedded signal processing systems and how those requirements are reflected in MPSoC architectures and the software developed for them. View full abstract»

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  • Multicore compilation strategies and challenges

    Publication Year: 2009 , Page(s): 55 - 63
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    To overcome challenges stemming from high power densities and thermal hot spots in microprocessors, multicore computing platforms have emerged as the ubiquitous computing platform from servers down through embedded systems. Unfortunately, providing multiple cores does not directly translate into increased performance or better energy efficiency for most applications. The burden is placed on software developers and tools to find and exploit coarse-grain parallelism to effectively make use of the abundance of computing resources provided by these systems. Concurrent applications are much more complex to develop than their single-threaded ancestors, thus software development tools will be critical to help programmers create both high performance and correct software. This article provides an overview of parallelism and compiler technology to help the community understand the software development challenges and opportunities for multicore signal processors. View full abstract»

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  • Multiprocessor SoC software design flows

    Publication Year: 2009 , Page(s): 64 - 71
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (558 KB) |  | HTML iconHTML  

    Typical design flows supporting the software development for multiprocessor systems are based on a board support package and high-level programming interfaces. These software design flows fail to support critical design activities, such as design space exploration or software synthesis. One can observe, however, that design flows based on a formal model of computation can overcome these limitations. In this article, we analyze the major challenges in multiprocessor software development and present a taxonomy of software design flows based on this analysis. Afterwards, we focus on design flows based on the Kahn process network (KPN) model of computation and elaborate on corresponding design automation techniques. We argue that the productivity of software developers and the quality of designs could be considerably increased by making use of these techniques. View full abstract»

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  • Multiprocessor SoC design methods and tools

    Publication Year: 2009 , Page(s): 72 - 79
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    Embedded software design for a multicore platform involves parallel programming for heterogeneous multiprocessors with diverse communication architectures under design constraints such as hardware cost, power, and timeliness. Since the classical von Neumann programming model assumes sequential execution of programs, it is not adequate for MPSoC SW development. Thus new programming models and corresponding SW development tools that are capable of exploiting the available parallelism and ensuring satisfaction of design constraints, are necessary. View full abstract»

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  • Multicore software technologies

    Publication Year: 2009 , Page(s): 80 - 89
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (578 KB) |  | HTML iconHTML  

    Multicore architectures require parallel computation and explicit management of the memory hierarchy, both of which add programming complexity and are unfamiliar to most programmers. While MPI and OpenMP still have a place in the multicore world, the learning curves are simply too steep for most programmers. New technologies are needed to make multicore processors accessible to a larger community. The signal and image processing community stands to benefit immensely from such technologies. This article provides a survey of new software technologies that hide the complexity of multicore architectures, allowing programmers to focus on algorithms instead of architectures. View full abstract»

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  • Discrete fourier transform on multicore

    Publication Year: 2009 , Page(s): 90 - 102
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    This article gives an overview on the techniques needed to implement the discrete Fourier transform (DFT) efficiently on current multicore systems. The focus is on Intel-compatible multicores, but we also discuss the IBM Cell and, briefly, graphics processing units (GPUs). The performance optimization is broken down into three key challenges: parallelization, vectorization, and memory hierarchy optimization. In each case, we use the Kronecker product formalism to formally derive the necessary algorithmic transformations based on a few hardware parameters. Further code-level optimizations are discussed. The rigorous nature of this framework enables the complete automation of the implementation task as shown by the program generator Spiral. Finally, we show and analyze DFT benchmarks of the fastest libraries available for the considered platforms. View full abstract»

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  • The parallelization of video processing

    Publication Year: 2009 , Page(s): 103 - 112
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    In this article, we focus on the applicability of parallel computing architectures to video processing applications. We demonstrate different optimization strategies in detail using the 3-D convolution problem as an example, and show how they affect performance on both many-core CPUs and symmetric multiprocessor CPUs. Applying these strategies to case studies from three video processing domains brings out some trends. The highly uniform, abundant parallelism in many video processing kernels means that they are well suited to a simple, massively parallel task-based model such as CUDA. As a result, we often see ten times or greater performances increases running on many-core hardware. Some kernels, however, push the limits of CUDA, because their memory accesses cannot be shaped into regular, vectorizable patterns or because they cannot be efficiently decomposed into small independent tasks. Such kernels, like the depth propagation kernel in the section "Synthesis Example: Depth Image-Based Rendering" may achieve a modest speedup, but they are probably better suited to a more flexible parallel programming model. We look forward to additional advances, as more researchers learn to harness the processing capabilities of the latest generation of computation hardware. View full abstract»

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  • Reconfigurable video coding on multicore

    Publication Year: 2009 , Page(s): 113 - 123
    Cited by:  Papers (12)
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    This article provides an overview of the main objectives of the new RVC standard, with an emphasis on the features that enable efficient implementation on platforms with multiple cores. A brief introduction to the methodologies that efficiently map RVC codec specifications to multicore platforms is accompanied with an example of the possible breakthroughs that are expected to occur in the design and deployment of multimedia services on multicore platforms. View full abstract»

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  • Parallel scalability in speech recognition

    Publication Year: 2009 , Page(s): 124 - 135
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1038 KB) |  | HTML iconHTML  

    We propose four application-level implementation alternatives called algorithm styles and construct highly optimized implementations on two parallel platforms: an Intel Core i7 multicore processor and a NVIDIA GTX280 manycore processor. The highest performing algorithm style varies with the implementation platform. On a 44-min speech data set, we demonstrate substantial speedups of 3.4 X on Core i7 and 10.5 X on GTX280 compared to a highly optimized sequential implementation on Core i7 without sacrificing accuracy. The parallel implementations contain less than 2.5% sequential overhead, promising scalability and significant potential for further speedup on future platforms. View full abstract»

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  • Connected operators

    Publication Year: 2009 , Page(s): 136 - 157
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3319 KB) |  | HTML iconHTML  

    Connected operators are filtering tools that act by merging elementary regions called flat zones. Connecting operators cannot create new contours nor modify their position. Therefore, they have very good contour-preservation properties and are capable of both low-level filtering and higher-level object recognition. This article gives an overview on connected operators and their application to image and video filtering. There are two popular techniques used to create connected operators. The first one relies on a reconstruction process. The operator involves first a simplification step based on a "classical" filter and then a reconstruction process. In fact, the reconstruction can be seen as a way to create a connected version of an arbitrary operator. The simplification effect is defined and limited by the first step. The examples we show include simplification in terms of size or contrast. The second strategy to define connected operators relies on a hierarchical region-based representation of the input image, i.e., a tree, computed in an initial step. Then, the simplification is obtained by pruning the tree, and, third, the output image is constructed from the pruned tree. This article presents the most important trees that have been used to create connected operators and also discusses important families of simplification or pruning criteria. We also give a brief overview on efficient implementations of the reconstruction process and of tree construction. Finally, the possibility to define and to use nonclassical notions of connectivity is discussed and illustrated. View full abstract»

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  • Rapid prototyping of radar algorithms [Applications Corner]

    Publication Year: 2009 , Page(s): 158 - 162
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    Rapid prototyping of advanced signal processing algorithms is critical to developing new radars. Signal processing engineers usually use high level languages like MATLAB, IDL, or Python to develop advanced algorithms and to determine the optimal parameters for these algorithms. Many of these algorithms have very long execution times due to computational complexity and/or very large data sets, which hinders an efficient engineering development workflow. That is, signal processing engineers must wait hours, or even days, to get the results of the current algorithm, parameters, and data set before making changes and refinements for the next iteration. In the meantime, the engineer may have thought of several more permutations that he or she wants to test. View full abstract»

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  • It depends on your point of view [Exploratory DSP]

    Publication Year: 2009 , Page(s): 163 - 168
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    Synthetic attendance-immersive communications with people in a meeting happening afar-has been one of mankind's elusive dreams. From the ill-fated picture phone to a current Second Life virtual world or a Cisco telepresence room, technologists have sought the Holy Grail for this universal desire. While recent progress has fueled euphoria, this article considers critical questions still awaiting resolution. View full abstract»

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  • Multiscale genomic imaging informatics [Life Sciences]

    Publication Year: 2009 , Page(s): 169-172, 180 - 180
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB) |  | HTML iconHTML  

    It is well known that the human genome has multiscale structures; multiscale approaches at the cellular, molecular, and sequence levels have been used to detect genomic variations, which are associated with phenotypic differences or diseases including cancers. Reaping the fruit of human genome sequencing, high-resolution imaging probes have been designed in recent years. Combined with image processing techniques, they enable the detection of cryptic and complex genetic aberrations at higher resolutions, holding great promise for personalized medicine. However, fulfilling the promise calls for powerful analytic techniques to handle the vast amount of imaging data generated by these high resolution imaging probes. Signal processing techniques such as wavelets play an important role in addressing computational challenges in this emerging area. View full abstract»

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  • Implicit human-centered tagging [Social Sciences]

    Publication Year: 2009 , Page(s): 173 - 180
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1555 KB) |  | HTML iconHTML  

    Tagging is the annotation of multimedia data with userspecified keywords known as tags, with the aim of facilitating fast and accurate data retrieval based on these tags. In contrast to this process, also referred to as explicit tagging, implicit human-centered tagging (IHCT) refers to exploiting the information on user's nonverbal reactions (e.g., facial expressions like smiles or head gestures like shakes) to multimedia data, with which he or she interacts, to assign new or improve the existing tags associated with the target data. Thus, implicit tagging allows that a data item gets tagged each time a user interacts with it based on the reactions of the user to the data (e.g., laughter when seeing a funny video), in contrast to explicit tagging paradigm in which a data item gets tagged only if a user is requested (or chooses) to associate tags with it. As nonverbal reactions to observed multimedia are displayed naturally and spontaneously, no purposeful explicit action (effort) is required from the user; hence, the resulting tagging process is said to be "implicit" and "human centered" (in contrast to being dictated by computer and being "computer-centered"). View full abstract»

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Aims & Scope

IEEE Signal Processing Magazine publishes tutorial-style articles on signal processing research and applications, as well as columns and forums on issues of interest.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Min Wu
University of Maryland, College Park
United States 

http://www/ece.umd.edu/~minwu/