IEEE Transactions on Circuits and Systems I: Regular Papers

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear sy... View full abstract»

In this paper, a signal processing methodology is proposed that performs delta-sigma (DeltaSigma) analog-to-digital (A/D) conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode (TM) signal processing, uses time-difference variables as an intermediate signal between the input voltage and the digital output. The resulting l... View full abstract»

A signal acquisition system is presented for the recording of small signals in the presence of low-frequency interference. In a conventional design, high-pass filters precede the input stage to remove the impeding signals. However, filters limit the recording bandwidth, can lead to long settling time after disturbance, and potentially valuable information about the interfering signal is removed. A... View full abstract»

This paper describes a technique for exploiting circuit instability to achieve baseband linear amplification. The input signal is periodically sampled by a first-order unstable circuit, and amplification is achieved by the exponentially growing natural response. A low-pass sampled amplifier response is achieved. An operational amplifier implementation of the circuit is described, and the main prac... View full abstract»

The self-powering, long-lasting, and functional features of embedded wireless microsensors appeal to an ever-expanding application space in monitoring, control, and diagnosis for military, commercial, industrial, space, and biomedical applications. Extended operational life, however, is difficult to achieve when power-intensive functions like telemetry draw whatever little energy is available from... View full abstract»

A previous cut-insertion theorem for linear circuits and its application to a generalization of the elementary feedback theory are further extended. The new theorem is based on the splitting of an arbitrary node into two nodes and on the insertion between them and another arbitrary ldquoreferencerdquo node, of a three-terminal circuit which keeps the network currents and voltages unchanged. The sy... View full abstract»

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers... View full abstract»

An high-speed special function unit (SFU) is presented in this paper. The system supports the single-precision IEEE-754 floating-point standard and implements faithfully rounded reciprocal, square root, reciprocal square root, logarithm, and exponential functions. The functions are approximated by using a novel constrained piecewise quadratic interpolation technique. In this way, the lookup table ... View full abstract»

Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We p... View full abstract»

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can be controlled, and we model the dissipated power of a processor as a positive and strictly increasing convex function of the speed. We show that ... View full abstract»

Modular exponentiation in public-key cryptosystems is usually achieved by repeated modular multiplications on large integers. Designing high-speed modular multiplication is thus very crucial to speed up the decryption/encryption process. In this paper, we first explore how to relax the data dependency that exists between multiplication, quotient determination, and modular reduction in the conventi... View full abstract»

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus (PLB) architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus (SLB), transforms an... View full abstract»

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of t... View full abstract»

We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay a... View full abstract»

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of t... View full abstract»

This paper presents two-step design methodologies and performance analyses of finite-impulse response (FIR), allpass, and infinite-impulse response (IIR) variable fractional delay (VFD) digital filters. In the first step, a set of fractional delay (FD) filters are designed. In the second step, these FD filter coefficients are approximated by polynomial functions of FD. The FIR FD filter design pro... View full abstract»

Bandwidth mismatch between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) causes undesirable distortions in the output spectrum. To reduce these undesired spectral components, methods are needed to estimate and correct the mismatch. In this paper, we introduce a hybrid filter-bank model of a two-channel time-interleaved ADC. The model allows the develop... View full abstract»

In this paper, a level-crossing analog-to-digital converter is described. It can convert audio bandwidth signals with high resolution using few threshold levels and digital interpolation. Samples are generated at nonuniform time intervals and then interpolated to produce uniformly spaced output samples. A periodic triangular dither signal added to the input ensures that low-amplitude or slowly var... View full abstract»

In this paper, a general complex switched network (CSN) model is presented. The model is more general than those in the literatures in which it contains switching behaviors on both its nodes and topology configuration. Robust stabilization of directed time-varying CSN with parametric uncertainties and two types of delays is investigated. The two types of delays consist of the system delay at each ... View full abstract»

We solve the problem of set-point (respectively, tracking) control of a permanent-magnet synchronous motor via linear time-invariant (respectively, time varying) control. Our control approach is based on the physical properties of the machine: inherent stability and robustness to external disturbances. Our analysis is carried out under mild conditions, using cascaded systems theory. ... View full abstract»

An N-symbol discrete Fourier transform (N -DFT) processor based on analog CMOS current mirrors that operate in the strong inversion region is presented. It is shown that transistor mismatch can be modeled as an input-referred noise source that can be used in system-level studies. Simulations of a radix-2, 256-symbol fast Fourier transform (FFT) show that the model produces equivalent... View full abstract»

Switched-capacitor (SC) converters are a type of variable structure systems. The conventional approach of maintaining regulation in these converters is a feedback control developed from linear systems theory, and it is based on the approximate small-signal linearized models of these circuits. However, the simplicity of such an approach sacrifices performance (poor transient response and sometimes ... View full abstract»