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# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 34

Publication Year: 2009, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers publication information

Publication Year: 2009, Page(s): C2
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• ### An 8$\times$8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-$\mu{\hbox{m}}$CMOS

Publication Year: 2009, Page(s):1541 - 1553
Cited by:  Papers (6)
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This paper presents an integrated 8 times 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 times 28 mum2, includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an i... View full abstract»

• ### Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas

Publication Year: 2009, Page(s):1554 - 1565
Cited by:  Papers (5)
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This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor i... View full abstract»

• ### A Low-Power Visual-Horizon Estimation Chip

Publication Year: 2009, Page(s):1566 - 1575
Cited by:  Papers (5)  |  Patents (1)
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Recent successes in the construction of micro aerial vehicles (&lt; 15 cm) have highlighted the lack of real-time sensors for flight control. This paper describes a low-power real-time visual-horizon sensor for stabilizing the pitch and roll of miniature aircraft in moderate-to-high-altitude flight. This prototype sensor uses a 12 times 12 photoreceptor array to find a best-fit horizon line ba... View full abstract»

• ### Subthreshold Parallel FM-to-Digital$\Delta$–$\Sigma$Converter With Output-Bit-Stream Addition by Interleaving

Publication Year: 2009, Page(s):1576 - 1589
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Single and parallel subthreshold frequency-modulation-to-digital Delta-Sigma modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional... View full abstract»

• ### Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits

Publication Year: 2009, Page(s):1590 - 1597
Cited by:  Papers (3)  |  Patents (7)
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This paper proposes a novel calculation method to derive self and mutual components of each segment in multiport inductors. In the proposed method, a set of S-parameters of the multiport inductor is mathematically decomposed into several matrices, which express self and mutual effects of each segment in the inductor. Due to this mathematics-based method, the multiport inductor can be characterized... View full abstract»

• ### Nanopower Subthreshold MCML in Submicrometer CMOS Technology

Publication Year: 2009, Page(s):1598 - 1611
Cited by:  Papers (12)  |  Patents (2)
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This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results a... View full abstract»

• ### A Digital PLL With a Stochastic Time-to-Digital Converter

Publication Year: 2009, Page(s):1612 - 1621
Cited by:  Papers (62)  |  Patents (2)
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A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS pro... View full abstract»

• ### Synchronization in a Multilevel CMOS Time-to-Digital Converter

Publication Year: 2009, Page(s):1622 - 1634
Cited by:  Papers (24)
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Accurate time-to-digital conversion is typically based on determining the positions of the timing signals within the period of an accurate clock with digital delay-line interpolators. In order to save circuit area and to improve single-shot precision to the picosecond level, multilevel interpolators can be used. Timing signals are generally asynchronous with respect to the main clock, and thus, in... View full abstract»

• ### Design of an All-Digital LVDS Driver

Publication Year: 2009, Page(s):1635 - 1644
Cited by:  Papers (10)
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This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mum 1P6M CMOS process with a core area of 0.07... View full abstract»

• ### A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

Publication Year: 2009, Page(s):1645 - 1656
Cited by:  Papers (10)
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A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operatio... View full abstract»

• ### Wide$V_{\rm DD}$Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems

Publication Year: 2009, Page(s):1657 - 1667
Cited by:  Papers (23)  |  Patents (3)
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Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failu... View full abstract»

• ### Pipeline Architectures for Radix-2 New Mersenne Number Transform

Publication Year: 2009, Page(s):1668 - 1680
Cited by:  Papers (17)
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Number theoretic transforms which operate in rings or fields of integers and use modular arithmetic operations can perform operations of convolution and correlation very efficiently and without round-off errors; thus, they are well matched to the implementation of digital filters. One such transform is the new Mersenne number transform, which relaxes the rigid relationship between the length of th... View full abstract»

• ### Robust Structure Transformation for Causal Lagrange-Type Variable Fractional-Delay Filters

Publication Year: 2009, Page(s):1681 - 1688
Cited by:  Papers (25)
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We have rigorously proved that an odd-order causal Lagrange-type variable fractional-delay (VFD) digital filter can be implemented as the Farrow structure with symmetric or antisymmetric subfilters through utilizing matrix transformation. This paper reveals a numerical problem that occurs in the matrix transformation due to the so-called catastrophic cancellation in numerical computation. Our comp... View full abstract»

• ### Phase Noise of a Class of Ring Oscillators Having Unsaturated Outputs With Focus on Cycle-to-Cycle Correlation

Publication Year: 2009, Page(s):1689 - 1707
Cited by:  Papers (8)
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This paper presents new theoretical results on the phase noise of a class of unsaturated ring oscillators. These new results focus on cycle-to-cycle correlation as a source of timing jitter and highlight its importance in contributing to the phase noise of these unsaturated ring oscillators. Because the outputs of saturated ring oscillators always reach the power supply, such cycle-to-cycle correl... View full abstract»

• ### Level-Crossing ADC Performance Evaluation Toward Ultrasound Application

Publication Year: 2009, Page(s):1708 - 1719
Cited by:  Papers (51)
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A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to t... View full abstract»

• ### Nonlinear-Observer-Based${\cal H}_{\infty}$Synchronization and Unknown Input Recovery

Publication Year: 2009, Page(s):1720 - 1731
Cited by:  Papers (25)
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The aim of this work is to provide a unified observer design method for nonlinear Lipschitz discrete-time systems with extension toHinfinsynchronization and input recovery used for communication systems. The stability analysis is performed using a suitable Lyapunov function that leads to the solvability of linear matrix inequalities. One of the main challenges is to establish non... View full abstract»

• ### Optimized Waveform Relaxation Methods for Longitudinal Partitioning of Transmission Lines

Publication Year: 2009, Page(s):1732 - 1743
Cited by:  Papers (26)
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Waveform relaxation (WR) is a technique that can be used to solve large systems of ordinary differential equations (ODEs). It is particularly suitable for the parallel solution of ODEs with multiple time scales and has successfully been used for the solution of electronic circuits and for solving partial differential equations. The main issue limiting the utility of WR is the class of problems wit... View full abstract»

• ### Robust Design of a Class of Time-Delay Iterative Learning Control Systems With Initial Shifts

Publication Year: 2009, Page(s):1744 - 1757
Cited by:  Papers (28)
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This paper is mainly devoted to the iterative learning control (ILC) design for time-delay systems (TDS) in the presence of initial shifts, especially when the system parameters are subject to polytopic-type uncertainties. The ILC laws using a pure error term and/or an initial rectifying action to address the initial shifts are considered, and the two-dimensional (2-D) system theory is employed to... View full abstract»

• ### Analysis of Internally Bandlimited Multistage Cubic-Term Generators for RF Receivers

Publication Year: 2009, Page(s):1758 - 1771
Cited by:  Papers (7)
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Adaptive feedforward error cancellation applied to correct distortion arising from third-order nonlinearities in RF receivers requires low-noise low-power reference cubic nonidealities. Multistage cubic-term generators utilizing cascaded nonlinear operations are ideal in this regard, but the frequency response of the interstage circuitry can introduce errors into the cubing operation. In this pape... View full abstract»

• ### Wideband, Bandpass, and Versatile Hybrid Filter Bank A/D Conversion for Software Radio

Publication Year: 2009, Page(s):1772 - 1782
Cited by:  Papers (37)
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This paper deals with analog-to-digital (A/D) conversion for future software/cognitive radio systems. For these applications, A/D converters should convert wideband signals and offer high resolutions. In order to achieve this and to overcome technological limitations, the A/D conversion systems should be versatile, i.e., it should be possible to adapt the conversion characteristics (resolution and... View full abstract»

• ### Guest Editorial Special Section on 2008 IEEE Custom Integrated Circuits Conference

Publication Year: 2009, Page(s):1783 - 1785
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• ### The Role of PLLs in Future Wireline Transmitters

Publication Year: 2009, Page(s):1786 - 1793
Cited by:  Papers (20)
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As data rates in wireline transmitters approach 80-100 Gb/s, phase-locked loops emerge as a serious bottleneck, requiring co-design of the clock and data paths. This paper describes speed, skew, and jitter issues at these rates and formulates the corruption due to effects such as the reference phase noise and the loop filter leakage. The phase noise performance of cascaded loops is also analyzed a... View full abstract»

• ### A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology

Publication Year: 2009, Page(s):1794 - 1806
Cited by:  Papers (7)  |  Patents (2)
| | PDF (3838 KB) | HTML

Pulse-width modulation pre-emphasis (PWM-PE) is a relatively new technique for compensating severe losses in wireline channels by varying the duty cycle of the transmitted pulse. The technique has been demonstrated upto 5 Gb/s and requires high-speed digital logic to accomodate narrow pulses in the transmitted bit stream. This work targets data rates beyond 10 Gb/s and extends PWM-PE to 4-PAM sign... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK