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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 5 • Date May 2009

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Displaying Results 1 - 25 of 28
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2009 , Page(s): C2
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  • Guest Editorial Special Issue on ISCAS 2008

    Publication Year: 2009 , Page(s): 861 - 864
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    Freely Available from IEEE
  • A Programmable 25-MHz to 6-GHz K/L Frequency Multiplier With Digital K_{\rm vco} Compensation

    Publication Year: 2009 , Page(s): 865 - 876
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1114 KB) |  | HTML iconHTML  

    A programmable rational-K/L frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 to 5.5 GHz is presented. The architecture employs a fractional-N input clock divider followed by a fractional- N PLL. In contrast to conventional architectures, this allows large K and L, whose maximum values are limited only by the word-length of digital SigmaDelta modulators. Additionally, to alleviate large K vco variation and fractional spurs, which are inevitable in wide tuning range VCOs and fractional-N synthesizers, new compensation techniques are implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on a field-programmable gate array. View full abstract»

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  • Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- N PLLs

    Publication Year: 2009 , Page(s): 877 - 885
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1878 KB) |  | HTML iconHTML  

    This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (????) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ???? fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-??m CMOS process. The fully-integrated ???? fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage. View full abstract»

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  • A Wideband Sigma-Delta Modulator With Cross-Coupled Two-Paths

    Publication Year: 2009 , Page(s): 886 - 893
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1163 KB) |  | HTML iconHTML  

    The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with N-path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology. View full abstract»

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  • A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

    Publication Year: 2009 , Page(s): 894 - 901
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2715 KB) |  | HTML iconHTML  

    This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-??m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within ??0.30 LSB and ??0.95 LSB, respectively. The ADC occupies an active die area of 0.56 mm2 and consumes 51.6 mW at a 1.2 V power supply. View full abstract»

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  • General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

    Publication Year: 2009 , Page(s): 902 - 910
    Cited by:  Papers (20)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (893 KB) |  | HTML iconHTML  

    Time-interleaved analog-to-digital converters (TIADCs) are sensitive to various mismatches that distort the sampled signal. Standard TIADC analysis assumes a narrowband sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived and are validated through simulations. In one of the examples presented, it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three. View full abstract»

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  • Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

    Publication Year: 2009 , Page(s): 911 - 919
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1633 KB) |  | HTML iconHTML  

    When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area. View full abstract»

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  • Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices

    Publication Year: 2009 , Page(s): 920 - 932
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1723 KB) |  | HTML iconHTML  

    This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To ensure a broadband input impedance matching, the g m-boosted topology has been chosen. Furthermore, the amplifiers have been designed to work over the whole UWB band (3.1-10.6 GHz), while driving a capacitive load, which is a realistic assumption for direct conversion receivers where the amplifier directly drives a mixer. The simulations (based on compact models obtained from preliminary measurements) highlight that, at the present stage of the technology development, the planar version of the circuit appears to outperform the FinFET one. The main reason is the superior cutoff frequency of planar devices in the inversion region, which allows the achievement of noise figure and voltage gain comparable to the FinFET counterpart, with a smaller power consumption. View full abstract»

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  • Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners

    Publication Year: 2009 , Page(s): 933 - 942
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1372 KB) |  | HTML iconHTML  

    This paper presents an electrostatic discharge (ESD)-protected ultra-wideband (UWB) low-noise amplifier (LNA) for full-band (170-to-1700 MHz) mobile TV tuners. It features a PMOS-based open-source input structure to optimize the I/O swings under a mixed-voltage ESD protection while offering an inductorless broadband input impedance match. The amplification core exploiting double current reuse and single-stage thermal-noise cancellation enhances the gain and noise performances with high power efficiency. Optimized in a 90-nm 1.2/2.5-V CMOS process with practical issues taken into account, the LNA using a constant-gm bias circuit achieves competitive and robust performances over process, voltage and temperature variation. The simulated voltage gain is 20.6 dB, noise figure is 2.4 to 2.7 dB, and IIP3 is +10.8 dBm . The power consumption is 9.6 mW at 1.2 V. |S11| < -10 dB is achieved up to 1.9 GHz without needing any external resonant network. Human Body Model ESD zapping tests of plusmn4 kV at the input pins cause no failure of any device. View full abstract»

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  • A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement

    Publication Year: 2009 , Page(s): 943 - 956
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2527 KB) |  | HTML iconHTML  

    Recent trends in the development of integrated silicon frequency sources are discussed. Within that context, a 25-MHz self-referenced solid-state frequency source is presented and demonstrated where measured performance makes it suitable for replacement of crystal oscillators (XOs) in data interface applications. The frequency source is referenced to a frequency-trimmed and temperature-compensated 800-MHz free-running LC oscillator (LCO) that is implemented in a standard logic CMOS process and with no specialized analog process options. Mechanisms giving rise to frequency drift in integrated LCOs are discussed and supported by analytical expressions. Design objectives and a compensation technique are presented where several implementation challenges are uncovered. Fabricated in a 0.25-mum 1P5M CMOS process, and with no external components, the prototype frequency source dissipates 59.4 mW while maintaining plusmn152 ppm frequency inaccuracy over process, plusmn 10% variation in the power supply voltage, and from - 10degC to 80degC. Variation against other environmental factors is also presented. Nominal period jitter and power-on start-up latency are 2.75 psrms and 268 mus, respectively. These performance metrics are compared with an XO at the same frequency. View full abstract»

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  • A 0.3-mW/Ch 1.25 V Piezo-Resistance Digital ROIC for Liquid-Dispensing MEMS

    Publication Year: 2009 , Page(s): 957 - 965
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1763 KB) |  | HTML iconHTML  

    A low-power multichannel CMOS digital read-out IC (ROIC) for differential piezo-resistive sensing is presented as part of the positioning system of a liquid dispensing MEMS. New very low-voltage and single-battery compatible CMOS circuits are proposed for digital gain tuning, pre-amplification, and integrating A/D conversion. Overall low-power consumption is achieved by operating the key devices in subthreshold in order to prevent from heating the fluidic MEMS. A complete quad-channel ROIC has been integrated in 0.35- ??m CMOS 2-polySi 4-metal technology. The reported experimental results agree with the electrical simulations. View full abstract»

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  • Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

    Publication Year: 2009 , Page(s): 966 - 974
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2838 KB) |  | HTML iconHTML  

    In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1?? VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications. View full abstract»

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  • A Fully Differential Rail-to-Rail CMOS Capacitance Sensor With Floating-Gate Trimming for Mismatch Compensation

    Publication Year: 2009 , Page(s): 975 - 986
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2108 KB) |  | HTML iconHTML  

    This paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances into rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the plusmn25-fF range, appropriate for sensing live cells using on-chip microelectrodes. An array architecture based on a shielded current routing bus has been developed for incorporating the capacitance measurement circuit into sensor arrays, with each pixel comprising four minimum-size digital transistors, enabling high-density integration. In addition to improving spatial resolution, the shielded current bus also eliminates the need for individual pixel calibration, conserves sensor evaluation speed, and provides protection from junction leakage. The sensor employs a 3-phase clocking scheme that enables on-chip gain tuning. The paper also presents a modified version of the sensor circuit incorporating floating-gate transistors for mismatch compensation and output offset cancellation, performed using a combination of impact-ionized channel hot electron injection and Fowler-Nordheim tunneling mechanisms. Chips comprising both versions of the sensor circuits in test arrays employing the shielded current routing bus were fabricated in a commercially available 2-poly, 3-metal, 0.5-mum CMOS process. The sensor operation was demonstrated by measuring on-chip test capacitances comprising single and interdigitated metal electrodes, configured using different capacitance compensation schemes. The differential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a resolution of 15 aF, and an output dynamic range of 65 dB. View full abstract»

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  • A Sub- \mu\hbox {W} Fully Tunable CMOS DPS for Uncooled Infrared Fast Imaging

    Publication Year: 2009 , Page(s): 987 - 996
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2201 KB) |  | HTML iconHTML  

    This paper presents a very low-power and fully programmable CMOS digital active pixel sensor for uncooled IR fast imaging. The proposed circuit topology includes self-biasing, built-in input capacitance compensation, predictive A/D conversion, and a truly digital I/O interface, all at pixel level. Furthermore, full fixed pattern noise cancellation is also supplied by the external digital tuning of both offset and gain for each individual pixel at no speed costs. Two DPS circuit implementations for IR PbSe sensors have been integrated in standard 0.35-mum 2-polySi 4-metal CMOS technology. Finally, exhaustive experimental results from their electrical tests are reported to validate the proposed DPS design techniques. View full abstract»

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  • Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

    Publication Year: 2009 , Page(s): 997 - 1004
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (594 KB) |  | HTML iconHTML  

    The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance. View full abstract»

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  • Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder

    Publication Year: 2009 , Page(s): 1005 - 1016
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1959 KB) |  | HTML iconHTML  

    Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2times2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2times2 traceback structure is implemented by using a 0.13-mum CMOS process in a core area of 7.16 mm2. Based on postlayout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration. View full abstract»

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  • A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

    Publication Year: 2009 , Page(s): 1017 - 1029
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1625 KB) |  | HTML iconHTML  

    We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings. View full abstract»

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  • An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers

    Publication Year: 2009 , Page(s): 1030 - 1040
    Cited by:  Papers (20)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1664 KB) |  | HTML iconHTML  

    This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in a 0.18-mum CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and the deviation from such a characteristic due to short channel effects and device mismatch is carefully considered in the paper. The squared signal is integrated using a Gm-C integrator that is interfaced with the squarer using a flipped voltage follower current sensor as a current to voltage converter. The proposed circuit dissipates 5.4 mW for a receiver sensitivity at the antenna of -89 dBm. Synchronization is demonstrated at the system level and some considerations on robustness to narrowband interferers are presented. View full abstract»

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  • Impulse-Based Scheme for Crystal-Less ULP Radios

    Publication Year: 2009 , Page(s): 1041 - 1052
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1066 KB) |  | HTML iconHTML  

    This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ??W with a clock generator inaccuracy of only 1%. View full abstract»

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  • Analysis and Design Techniques of CMOS Charge-Pump-Based Radio-Frequency Antenna-Switch Controllers

    Publication Year: 2009 , Page(s): 1053 - 1062
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB) |  | HTML iconHTML  

    Analysis and design techniques of charge-pump-based RF antenna-switch controllers are presented. Loading effects of RF antenna switches that cause voltage drop of the controller have been identified and embedded in the analysis. The proposed analysis also captures effects of MOS-switch on-resistance and parasitic capacitances, so more precise descriptions of the charge-pump output voltage can be obtained. Furthermore, the body biasing technique has been employed to prevent latch-up. The analysis and the design techniques have been verified using a 0.35-mum CMOS technology. RF antenna-switch performances with the designed controller have also been measured and presented. View full abstract»

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  • A 200-Mbps 0.02-nJ/b Dual-Mode Inductive Coupling Transceiver for cm-Range Multimedia Application

    Publication Year: 2009 , Page(s): 1063 - 1072
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2796 KB) |  | HTML iconHTML  

    A 200-Mbps 0.02-nJ/b dual-mode inductive coupling transceiver is proposed for cm-range multimedia application. The inductive link geometry and the advantage of the pulse-based inductive coupling are explained. In this paper, the parallel capacitor connected with the TX inductor, the intersymbol interference (ISI) reduction scheme, and the pulse generation scheme are newly proposed. The parallel capacitor connected with the TX inductor increases the transmitter impedance so that it enhances the transmission distance by twofold, and the ISI reduction scheme pushes data rate up to 200 Mbps. Moreover, the pulse generation scheme reduces the energy consumption as low as 0.02 nJ/b. Maximum data rate and energy consumption are achieved in simulation. The transceiver occupies 0.012 mm2 in 0.25-mum CMOS process. View full abstract»

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  • ICECS 2009

    Publication Year: 2009 , Page(s): 1073
    Save to Project icon | Request Permissions | PDF file iconPDF (644 KB)  
    Freely Available from IEEE
  • 2010 IEEE International Symposium on Circuits and Systems (ISCAS2010)

    Publication Year: 2009 , Page(s): 1074
    Save to Project icon | Request Permissions | PDF file iconPDF (701 KB)  
    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras