2009 10th International Symposium on Quality Electronic Design

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI P... View full abstract»

A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model. View full abstract»

This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread. View full abstract»

As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage p... View full abstract»

We describe here, the design and use of a unique test chip on power and variability (TPV) to measure and report for the first time, the magnitude of leakage and dynamic power dissipation and its variation. This test chip, fabricated in a state-of-the-art 45 nm process node technology, addresses the important issues of variability in power and delay and quantifies them as a function of voltage and ... View full abstract»

We are proposing an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern (4Cc and 3Cc) induced delay in bus-based macro-cell designs. The crosstalk patterns are classified as 4Cc, 3Cc, 2Cc, and Cc based on Miller coupling effect (MCF). The proposed technique implements a crosstalk pattern detection unit to detect the occurrence of worst-case crosstalk patterns by comp... View full abstract»

Differential signaling is widely used in high speed data communications. Inter-symbol interference (ISI) and crosstalk between differential pair, however, heavily affect the integrity of differential signaling as measured by timing jitter and amplitude noise in the eye diagram. To reduce the impact of ISI, a pre-emphasis filter is commonly used, but it increases the crosstalk noise. In this paper,... View full abstract»

The semiconductor industry is headed towards a new era of scaling and uncertainty with new key building blocks for the next-generation chips, the high-kappa metal-gate transistor. There is a need for statistical characterization of high-kappa metal-gate digital gates as a function of process parameter variations to make them available for designers. In this paper, we present a methodology for PVT ... View full abstract»

Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. Reducing the library size is becoming a must. In this paper, we present an efficient piece-wise nonlinear library modeling format and library size reduction technique. Instead of using tables and vectors, this format uses base templates (cu... View full abstract»

Recently, a transistor level dual-V_th technique has been proposed, where transistors within the same cell are allowed to have different V_th to form the so-call mixed V_th (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual V_th design flow. To make this ... View full abstract»

Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability. The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge. SSTA is suitable for timing estimation and design for manufacturability under process variation. However, most of the existing SS... View full abstract»

For timing analysis, each flip-flop and latch in a standard library is characterized for two constraints: setup time and hold time constraints. These constraints need to be characterized for their sensitivities to the variation parameters in order to perform statistical timing analysis. Several approaches have been proposed to perform statistical characterization of delays. However, the predominan... View full abstract»

This paper describes PETE, a tool that has been developed for circuit/system level evaluation of nanoscaled devices. The motivation behind developing this tool is the fact that traditional device metrics like CV/Ion, Ioff or CV²f can no longer capture the true potential of semiconductor devices and underestimate or overestimate system level performance. At the same time, the... View full abstract»

Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture... View full abstract»

This paper presents an accurate and fully analytical model of delay in subthreshold inverters. The model characterizes the direct connection between the input slew and output delay. It is also capable of predicting the signal slew at the inverter output. Delay and slew prediction models are used to compute delay and understand slew propagation in an inverter chain. These models can also provide in... View full abstract»