16-18 March 2009
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[Front cover]
Publication Year: 2009, Page(s): c1|
PDF (265 KB)
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[Title page]
Publication Year: 2009, Page(s): i|
PDF (73 KB)
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[Copyright notice]
Publication Year: 2009, Page(s): ii|
PDF (92 KB)
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Welcome to ISQED'09
Publication Year: 2009, Page(s): iii -
Best papers
Publication Year: 2009, Page(s): iv|
PDF (109 KB)
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Quality award
Publication Year: 2009, Page(s): v|
PDF (119 KB)
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Quality award
Publication Year: 2009, Page(s): vi|
PDF (120 KB)
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Organizing Committee
Publication Year: 2009, Page(s):vii - xiii|
PDF (86 KB)
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ISQED 2009 conference at a glance
Publication Year: 2009, Page(s): xiv|
PDF (2329 KB)
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Table of content
Publication Year: 2009, Page(s):xv - xxiv|
PDF (211 KB)
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Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
Publication Year: 2009, Page(s):1 - 6
Cited by: Papers (34) | Patents (1)On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI P... View full abstract»
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A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability
Publication Year: 2009, Page(s):7 - 12
Cited by: Papers (5)A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model. View full abstract»
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NBTI-aware statistical circuit delay assessment
Publication Year: 2009, Page(s):13 - 18
Cited by: Papers (4)This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread. View full abstract»
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On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
Publication Year: 2009, Page(s):19 - 26
Cited by: Papers (32)As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage p... View full abstract»
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Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design
Publication Year: 2009, Page(s):27 - 32We describe here, the design and use of a unique test chip on power and variability (TPV) to measure and report for the first time, the magnitude of leakage and dynamic power dissipation and its variation. This test chip, fabricated in a state-of-the-art 45 nm process node technology, addresses the important issues of variability in power and delay and quantifies them as a function of voltage and ... View full abstract»
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On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs
Publication Year: 2009, Page(s):33 - 39
Cited by: Papers (3)We are proposing an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern (4Cc and 3Cc) induced delay in bus-based macro-cell designs. The crosstalk patterns are classified as 4Cc, 3Cc, 2Cc, and Cc based on Miller coupling effect (MCF). The proposed technique implements a crosstalk pattern detection unit to detect the occurrence of worst-case crosstalk patterns by comp... View full abstract»
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Worst case timing jitter and amplitude noise in differential signaling
Publication Year: 2009, Page(s):40 - 46
Cited by: Papers (3)Differential signaling is widely used in high speed data communications. Inter-symbol interference (ISI) and crosstalk between differential pair, however, heavily affect the integrity of differential signaling as measured by timing jitter and amplitude noise in the eye diagram. To reduce the impact of ISI, a pre-emphasis filter is commonly used, but it increases the crosstalk noise. In this paper,... View full abstract»
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A PVT aware accurate statistical logic library for high-κ metal-gate nano-CMOS
Publication Year: 2009, Page(s):47 - 54
Cited by: Papers (5)The semiconductor industry is headed towards a new era of scaling and uncertainty with new key building blocks for the next-generation chips, the high-kappa metal-gate transistor. There is a need for statistical characterization of high-kappa metal-gate digital gates as a function of process parameter variations to make them available for designers. In this paper, we present a methodology for PVT ... View full abstract»
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A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis
Publication Year: 2009, Page(s):55 - 61Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. Reducing the library size is becoming a must. In this paper, we present an efficient piece-wise nonlinear library modeling format and library size reduction technique. Instead of using tables and vectors, this format uses base templates (cu... View full abstract»
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Leakage optimization using transistor-level dual threshold voltage cell library
Publication Year: 2009, Page(s):62 - 67
Cited by: Papers (4)Recently, a transistor level dual-V<sub>th</sub> technique has been proposed, where transistors within the same cell are allowed to have different V<sub>th</sub> to form the so-call mixed V<sub>th</sub> (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual V<sub>th</sub> design flow. To make this ... View full abstract»
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Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution
Publication Year: 2009, Page(s):68 - 73
Cited by: Papers (3)Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability. The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge. SSTA is suitable for timing estimation and design for manufacturability under process variation. However, most of the existing SS... View full abstract»
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Characterization of sequential cells for constraint sensitivities
Publication Year: 2009, Page(s):74 - 79
Cited by: Papers (3) | Patents (2)For timing analysis, each flip-flop and latch in a standard library is characterized for two constraints: setup time and hold time constraints. These constraints need to be characterized for their sensitivities to the variation parameters in order to perform statistical timing analysis. Several approaches have been proposed to perform statistical characterization of delays. However, the predominan... View full abstract»
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PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices
Publication Year: 2009, Page(s):80 - 85
Cited by: Papers (8)This paper describes PETE, a tool that has been developed for circuit/system level evaluation of nanoscaled devices. The motivation behind developing this tool is the fact that traditional device metrics like CV/Ion, Ioff or CV2f can no longer capture the true potential of semiconductor devices and underestimate or overestimate system level performance. At the same time, the development... View full abstract»
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Architecture design exploration of three-dimensional (3D) integrated DRAM
Publication Year: 2009, Page(s):86 - 90
Cited by: Papers (15) | Patents (4)Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture... View full abstract»
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Accurate buffer modeling with slew propagation in subthreshold circuits
Publication Year: 2009, Page(s):91 - 96
Cited by: Papers (11)This paper presents an accurate and fully analytical model of delay in subthreshold inverters. The model characterizes the direct connection between the input slew and output delay. It is also capable of predicting the signal slew at the inverter output. Delay and slew prediction models are used to compute delay and understand slew propagation in an inverter chain. These models can also provide in... View full abstract»