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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 8 • Date Sept. 2008

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Displaying Results 1 - 25 of 30
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2008 , Page(s): C2
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    Freely Available from IEEE
  • Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC

    Publication Year: 2008 , Page(s): 2157 - 2165
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1341 KB) |  | HTML iconHTML  

    The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on- chips (SoCs), requires that digital and analog blocks be merged into single chips. High resolution digital-analog converters (DACs) are especially sensitive to the final matching of components and their nominal accuracy is typically enhanced with additional calibration circuitry or laser trimming. Additional calibration circuits increase cost significantly and mainstream laser trimming technique is applied on thin film resistive layers that are not available with most standard fabrication processes used for SoC. In this paper, we present a high-resolution DAC taking advantage of a new laser trimming technique which is compatible with standard CMOS processes, and that can be integrated in SoCs. While initial mismatch prevents reaching the targeted 14-bit resolution, the included tuning elements offer the necessary calibration to exceed the matching requirements and obtain the desired DAC linearity. The architecture of the DAC itself is a classic current-mode segmented resistor ladder: an inverted R2R ladder generating the binary weighted least significant bit currents is combined with unary current sources for the thermometer encoded most significant bits. The entire structure is precisely calibrated to obtain the final desired linearity. The effectiveness of the trimming technology and its application to high-accuracy DACs is demonstrated. View full abstract»

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  • A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS

    Publication Year: 2008 , Page(s): 2166 - 2177
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3889 KB) |  | HTML iconHTML  

    A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-mum 25-GHz fT complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input range at 2-MHz input frequency. The 5 times 5.3 mm2 die consumes 1.7 W from a dual plusmn2.7-V supply. A noniterative analog auto-calibration algorithm simultaneously compensates for both random mismatch in the capacitors of the first quantizer stages, and integral nonlinearity curvatures contributed by sample-and-hold (S/H) and voltage reference buffers, yielding SFDR optimizations up to 12 dB. The test chip performance validates the transient noise simulations run for the analog front-end and the clock jitter, corroborating the efficacy of the circuit techniques adopted to design S/H, clock and references. View full abstract»

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  • A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

    Publication Year: 2008 , Page(s): 2178 - 2187
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1760 KB) |  | HTML iconHTML  

    This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted because of the signal-dependent voltage change at the current input terminal, and it is linearized by injecting a current that is proportional to the signal-dependent voltage change at the current input terminal, into the same current input terminal of the current-mode circuit. A current-mode sample-and-hold amplifier (SHA) that adopts the proposed scheme was fabricated and a 0.35-mum CMOS process was used to verify the effectiveness of the scheme. It operated from a 2-V supply voltage in the analog part and a 2.5 V in the digital part with a 100-MHz clock and realized a 77- and a 86-dB spurious-free dynamic range values for 0 and -10 dB of full-scale signal current level (plusmn100 muA), respectively, of the 1-MHz signal input. More than a 13-bit equivalent SFDR for -14 to -4 dB of full-scale input was obtained, proving the effectiveness of the proposed scheme at realizing distortionless signal current processing. View full abstract»

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  • Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps

    Publication Year: 2008 , Page(s): 2188 - 2201
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB) |  | HTML iconHTML  

    This paper presents several comprehensive and novel circuit techniques that can be efficiently applied to low-voltage (LV) high-speed reset-opamp (RO) and switched-opamp (SO) in LV switched-capacitor circuits. The first, designated as virtual-ground common-mode (CM) feedback with output CM error correction, allows the design of fully differential RO circuits that could only be traditionally implemented before in pseudo-differential mode, and it leads to considerable savings of half of the opamps' power. The second, uses a crossed-coupled passive sampling interface to avoid the extra track-and-reset stages as required in both RO and SO circuits, further saving one front-end opamp's power. The third, employs a voltage-controlled level-shifting (LS) technique that utilizes the charge redistribution property to process the CM LS in an LV environment, avoiding the degradation of the feedback factor by the use of extra LS circuits. Finally, the fourth, the LV finite-gain compensation technique allows the use of low-gain high-speed single-stage amplifier in contrast to the conventional high-gain, low-speed two-stage opamp to achieve a high-speed operation in both RO and SO circuits. Without any clock boosting or bootstrap circuits, all of the above techniques can be applied in LV applications without any floating switches limitations. Measurement results of a 1.2-V 10-bit 60 MS/s pipelined analog-digital converter in 0.18- mum CMOS with RO are presented to verify the effectiveness of the proposed techniques, achieving a signal-to-noise distortion ratio of 55.2 dB with 85-mW power consumption. View full abstract»

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  • Wire Optimization for Multimedia SoC and SiP Designs

    Publication Year: 2008 , Page(s): 2202 - 2215
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2275 KB) |  | HTML iconHTML  

    With advances in VLSI integration technology, a large number of hardware components can be integrated into a single chip. To provide the communication bandwidth for these components, existing bus-based interconnects often suffer from a large area occupied by a large number of bus signals. To address this issue, this paper proposes a new protocol for on-chip or in-package communication that is termed the system-on-chip network protocol (SNP). SNP uses a small number of signals that are shared by address, control, and data information. Additional three-bit phase signals are used to distinguish the different information transmitted through a single set of SNP signals. Two sets of identical SNP signals form a symmetric communication channel that allow a master-to-master type of communication between hardware components. The phase signals facilitate the reduction of the communication time with phase interleaving and phase omission-restoration among successive transactions. The efficiency of SNP is evaluated by a static performance analysis as well as by simulations with register-transfer level models of SNP components. Both the analysis and simulation results show that the communication time with SNP is approximately a half that of advanced microcontroller bus architecture advanced high-performance bus (AHB), although SNP has wires that are approximately three-fifths of AHB. MPEG-4 chips are implemented with both AHB and SNP, respectively, and it is observed from the MPEG-4 implementations that SNP requires less area for communication compared to AHB. View full abstract»

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  • Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

    Publication Year: 2008 , Page(s): 2216 - 2225
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1170 KB) |  | HTML iconHTML  

    This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- mum CMOS process using a resolution of 640 × 480. A maximum SE of 63 × 63 is supported at an estimated clock frequency of 333 MHz. View full abstract»

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  • A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System

    Publication Year: 2008 , Page(s): 2226 - 2237
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1429 KB) |  | HTML iconHTML  

    This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of plusmn10 kHz. The linearity at the range of 27 MHz plusmn10 kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 mm2 in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip. View full abstract»

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  • Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits

    Publication Year: 2008 , Page(s): 2238 - 2248
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1647 KB) |  | HTML iconHTML  

    In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-nor circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100times. View full abstract»

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  • Energy, Performance, and Probability Tradeoffs for Energy-Efficient Probabilistic CMOS Circuits

    Publication Year: 2008 , Page(s): 2249 - 2262
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1236 KB) |  | HTML iconHTML  

    The scaling trend of semiconductor devices has raised several issues such as energy consumption and heat dissipation, as well as the increasing probabilistic behavior of devices. Motivated by the necessity to consider probabilistic approaches to future designs, probabilistic CMOS (PCMOS) based computing has been proposed. PCMOS devices are inherently probabilistic devices that compute correctly with a probability p. This paper investigates the tradeoffs between the energy, speed (or performance), and probability of correctness (p) of PCMOS circuits. For given constraints on p, performance, and energy delay product (EDP), and using analytical models of energy, delay, and p, the optimum values of EDP and probability are found for PCMOS circuits. The analytical models are validated using circuit simulations for PCMOS circuits designed in a 0.13-mum process. The results show that, to minimize EDP, it is preferable to operate PCMOS circuits at lower supply voltages. On the other hand, to maximize p, the highest possible supply voltage under the given constraints is preferable. Our analysis makes it possible to achieve an optimal circuit design that satisfies the p , performance, and EDP requirements for a given application. An analysis of the impact of variations in temperature, threshold voltage, and supply voltage on optimal EDP and probability values is also included. View full abstract»

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  • A Clock-Less Jitter Spectral Analysis Technique

    Publication Year: 2008 , Page(s): 2263 - 2272
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2509 KB) |  | HTML iconHTML  

    In this paper, we propose a method for extracting the spectral information of a multigigahertz jittery signal without using an ideal reference clock. This method utilizes existing on-chip single-shot period measurement techniques to measure single periods of a multigigahertz signal for analysis. Utilizing the same sampling and measuring principle, we propose another less computationally intensive method, based on the derivative principle, to extract only the random jitter component of the signal. To perform analysis on higher frequency signals, both methods are extended to measures multiple signal periods, instead of a single period, at each sampling. These methods do not require an ideal sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that these methods can accurately estimate the sinusoidal and random jitters of a multigigahertz signal. Extracted values can be used for estimating the bit-error rate of serial communication systems. View full abstract»

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  • Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator–Multiplier Cascade

    Publication Year: 2008 , Page(s): 2273 - 2286
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (611 KB) |  | HTML iconHTML  

    This paper considers the problem of reconstructing a bandlimited signal from its nonuniform samples. Based on a discrete-time equivalent model for nonuniform sampling, we propose the differentiator-multiplier cascade, a multistage reconstruction system that recovers the uniform samples from the nonuniform samples. Rather than using optimally designed reconstruction filters, the system improves the reconstruction performance by cascading stages of linear-phase finite impulse response (FIR) filters and time-varying multipliers. Because the FIR filters are designed as differentiators, the system works for the general nonuniform sampling case and is not limited to periodic nonuniform sampling. To evaluate the reconstruction performance for a sinusoidal input signal, we derive the signal-to-noise-ratio at the output of each stage for the two-periodic and the general nonuniform sampling case. The main advantage of the system is that once the differentiators have been designed, they are implemented with fixed multipliers, and only some general multipliers have to be adapted when the sampling pattern changes; this reduces implementation costs substantially, especially in an application like time-interleaved analog-to-digital converters (TI-ADCs) where the timing mismatches among the ADCs may change during operation. View full abstract»

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  • On the Polyphase Decomposition for Design of Generalized Comb Decimation Filters

    Publication Year: 2008 , Page(s): 2287 - 2299
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (683 KB) |  | HTML iconHTML  

    Generalized comb filters (GCFs) are efficient anti-aliasing decimation filters with improved selectivity and quantization noise (QN) rejection performance around the so called folding bands with respect to classical comb filters. In this paper, we address the design of GCF filters by proposing an efficient partial polyphase architecture with the aim to reduce the data rate as much as possible after the SigmaDelta A/D conversion. We propose a mathematical framework in order to completely characterize the dependence of the frequency response of GCFs on the quantization of the multipliers embedded in the proposed filter architecture. This analysis paves the way to the design of multiplier-less decimation architectures. We also derive the impulse response of a sample third-order GCF filter used as reference scheme throughout the paper. View full abstract»

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  • Digital IIR Integrator Design Using Richardson Extrapolation and Fractional Delay

    Publication Year: 2008 , Page(s): 2300 - 2309
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    In this paper, a new design of digital integrator is investigated. First, the trapezoidal integration rule and differential equation are applied to derive the transfer function of the digital integrator. The Richardson extrapolation is then used to generate high-accuracy results while using low-order formulas. Next, the conventional Lagrange finite-impulse response fractional delay filter is directly applied to implement the designed integrator. Two implementation structures are studied: direct substitution and polyphase decomposition. Finally, numerical comparisons with conventional digital integrators are made to demonstrate the effectiveness of this new design approach. View full abstract»

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  • Information Theoretic Approach to Complexity Reduction of FIR Filter Design

    Publication Year: 2008 , Page(s): 2310 - 2321
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1181 KB) |  | HTML iconHTML  

    This paper presents a new paradigm of design methodology to reduce the complexity of application-specific finite-impulse response (FIR) digital filters. A new adder graph data structure called the multiroot binary partition graph (MBPG) is proposed for the formulation of the multiple constant multiplication problem of FIR filter design. The set of coefficients in any fixed point representation is partitioned into symbols so that common subexpression identification and elimination become congruent to information parsing for data compression. A minimum number of different pairs or groups of symbols and residues can be used to code a set of coefficients based on their probability and conditional probability of occurrence. This ingenious concept enables the notion of entropy to be applied as a quantitative measure to evaluate the coding density of different compositions of symbols towards a set of coefficients. The minimal vertex set MBPG synthesized by our proposed information theoretic approach results in direct correspondences between the vertices and adders, and edges and physical interconnections. Unlike the common subexpression elimination algorithms based on other graph data structures, the symbol-level information carried in each vertex and the graph isomorphism of MBPG promise further fine-grain optimization in a reduced search space. One such optimization that has been exploited in this paper is the shift-inclusive computation reordering to minimize the width of every two's complement adder to further reduce the implementation cost and the critical path delay of the filter. Experiment results show that the proposed algorithm can contribute up to 19.30% reductions in logic complexity and up to 61.03% reduction in critical path delay over other minimization methods. View full abstract»

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  • A Lattice Structure of Biorthogonal Linear-Phase Filter Banks With Higher Order Feasible Building Blocks

    Publication Year: 2008 , Page(s): 2322 - 2331
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (826 KB) |  | HTML iconHTML  

    This paper proposes a lattice structure of biorthogonal linear-phase filter banks (BOLPFBs) using new building blocks which can obtain long filters with fewer number of building blocks than conventional ones. The structure is derived from a generalization of the building blocks of first-order LPFBs. Furthermore, the proposed building blocks are applicable for both even and odd number of channels. The resulting FBs have good performance in stopband attenuation and low implementation costs. View full abstract»

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  • Ultrafast Analog Fourier Transform Using 2-D LC Lattice

    Publication Year: 2008 , Page(s): 2332 - 2343
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3612 KB) |  | HTML iconHTML  

    We describe how a 2-D rectangular lattice of inductors and capacitors can serve as an analog Fourier transform device, generating an approximate discrete Fourier transform (DFT) of an arbitrary input vector of fixed length. The lattice displays diffractive and refractive effects and mimics the combined optical effects of a thin-slit aperture and lens. Diffraction theories in optics are usually derived for 3-D media, whereas our derivations proceed in 2-D. Analytical and numerical results show agreement between lattice output and the true DFT. Potentially, this lattice can be used for an extremely low latency and high throughput analog signal processing device. The lattice can be fabricated on-chip with frequency of operation of more than 10 GHz. View full abstract»

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  • Blind-Channel Estimation for MIMO Systems With Structured Transmit Delay Scheme

    Publication Year: 2008 , Page(s): 2344 - 2355
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1007 KB) |  | HTML iconHTML  

    This paper considers blind-channel estimation for multiple-input multiple-output (MIMO) systems with structured transmitter design. First, a structured transmit delay (STD) scheme is proposed for MIMO systems. Unlike existing transmit diversity approaches, in which different antennas transmit delayed, zero padded, or time-reversed versions of the same signal, in the proposed scheme, each antenna transmits an independent data stream, therefore promises higher data rate and more flexibility to transmitter design. Second, second-order statistics based blind-channel estimation algorithms are developed for MIMO systems with STD scheme. Channel identifiability is addressed for both correlation-based and subspace-based approaches. The proposed approaches involve no pre-equalization, have no limitations on channel zero locations, and do not rely on nonconstant modulus precoding. Third, when channel coding is employed, estimation accuracy can be further enhanced through ldquopostprocessingrdquo, in which channel estimation is refined by taking the tentative decisions from the channel decoder as pseudo-training symbols. Simulation examples are provided to demonstrate the robustness and effectiveness of the proposed approaches. View full abstract»

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  • Nonnegative Matrix Factorization Applied to Nonlinear Speech and Image Cryptosystems

    Publication Year: 2008 , Page(s): 2356 - 2367
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2002 KB) |  | HTML iconHTML  

    Nonnegative matrix factorization (NMF) is widely used in signal separation and image compression. Motivated by its successful applications, we propose a new cryptosystem based on NMF, where the nonlinear mixing (NLM) model with a strong noise is introduced for encryption and NMF is used for decryption. The security of the cryptosystem relies on following two facts: 1) the constructed multivariable nonlinear function is not invertible; 2) the process of NMF is unilateral, if the inverse matrix of the constructed linear mixing matrix is not nonnegative. Comparing with Lin's method (2006) that is a theoretical scheme using one-time padding in the cryptosystem, our cipher can be used repeatedly for the practical request, i.e., multitme padding is used in our cryptosystem. Also, there is no restriction on statistical characteristics of the ciphers and the plaintexts. Thus, more signals can be processed (successfully encrypted and decrypted), no matter they are correlative, sparse, or Gaussian. Furthermore, instead of the number of zero-crossing-based method that is often unstable in encryption and decryption, an improved method based on the kurtosis of the signals is introduced to solve permutation ambiguities in waveform reconstruction. Simulations are given to illustrate security and availability of our cryptosystem. View full abstract»

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  • Quantum-Noise Limited Distance Resolution of Optical Range Imaging Techniques

    Publication Year: 2008 , Page(s): 2368 - 2377
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    The most common optical distance imaging methods (triangulation, interferometry and time-of-flight ranging) can all be described in a unified way as linear shift-invariant systems in which the determination of distance corresponds to the measurement of a spatial or temporal phase. Since the ultimate precision of such a phase measurement is limited by quantum noise of the involved photons or photocharges, the eventual distance resolution of the three optical ranging methods depends in the same way on quantum noise. Evidence from literature supports our basic assertion that photon and photocharge numbers have a Poisson distribution under most experimental conditions. This allows us to derive our main result that the quantum-noise limited distance resolution of the three optical ranging methods is proportional to the inverse of the signal's modulation amplitude times the square root of the background level. The equation for the precision of the three optical distance measurement techniques contains the method's experimental parameters in a single factor, from which the optimum distance range of the three techniques can easily be deduced: 1 nm-1 mum for interferometry, 1 mum-10 m for triangulation, > 0.1 m for time-of-flight ranging, if visible or near infrared light is used. View full abstract»

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  • Subgradient-Based Neural Networks for Nonsmooth Convex Optimization Problems

    Publication Year: 2008 , Page(s): 2378 - 2391
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB) |  | HTML iconHTML  

    This paper develops a neural network for solving the general nonsmooth convex optimization problems. The proposed neural network is modeled by a differential inclusion. Compared with the existing neural networks for solving nonsmooth convex optimization problems, this neural network has a wider domain for implementation. Under a suitable assumption on the constraint set, it is proved that for a given nonsmooth convex optimization problem and sufficiently large penalty parameters, any trajectory of the neural network can reach the feasible region in finite time and stays there thereafter. Moreover, we can prove that the trajectory of the neural network constructed by a differential inclusion and with arbitrarily given initial value, converges to the set consisting of the equilibrium points of the neural network, whose elements are all the optimal solutions of the primal constrained optimization problem. In particular, we give the condition that the equilibrium point set of the neural network coincides with the optimal solution set of the primal constrained optimization problem and the condition ensuring convergence to the optimal solution set in finite time. Furthermore, illustrative examples show the correctness of the results in this paper, and the good performance of the proposed neural network. View full abstract»

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  • Two-Parameter Discontinuity-Induced Bifurcation Curves in a ZAD-Strategy-Controlled DC–DC Buck Converter

    Publication Year: 2008 , Page(s): 2392 - 2401
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB) |  | HTML iconHTML  

    The dynamics of a zero-average dynamic strategy controlled dc-dc Buck converter, modelled by a set of differential equations with discontinuous right-hand side is studied. Period-doubling and corner-collision bifurcations are found to occur close to each other under small parameter variations. Closer examination of the parameter space leads to the discovery of a novel bifurcation. This type of bifurcation has not been reported so far in the literature and it corresponds to a corner-collision bifurcation of a nonhyperbolic cycle. The bifurcation boundaries are computed analytically in this paper and the system dynamics are unfolded close to the novel bifurcation point. View full abstract»

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  • Optimal Synthesis of State-Estimate Feedback Controllers With Minimum l_{2} -Sensitivity

    Publication Year: 2008 , Page(s): 2402 - 2410
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (377 KB) |  | HTML iconHTML  

    This paper investigates the problem of synthesizing the optimal structure of a state-estimate feedback controller with minimum l 2-sensitivity and no overflow. First, the l 2-sensitivity of a closed-loop transfer function with respect to the coefficients of a state-estimate feedback controller is analyzed. Next, two iterative techniques for obtaining the coordinate transformation matrix which constructs the optimal structure of a state-estimate feedback controller are developed so as to minimize an l 2-sensitivity measure subject to l 2-scaling constraints. One technique is based on a Lagrange function, some matrix-theoretic techniques, and an efficient bisection method. Another technique converts the problem into an unconstrained optimization formulation by using linear-algebraic techniques, and optimizes it by applying an efficient quasi-Newton method with closed-form formula for gradient evaluation. A numerical example is also presented to illustrate the utility of the proposed techniques. View full abstract»

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  • Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

    Publication Year: 2008 , Page(s): 2411 - 2422
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1474 KB) |  | HTML iconHTML  

    This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13-mum CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras