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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 6 • Date July 2008

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Displaying Results 1 - 25 of 42
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2008 , Page(s): C2
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    Freely Available from IEEE
  • Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance

    Publication Year: 2008 , Page(s): 1405 - 1411
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1823 KB) |  | HTML iconHTML  

    A photodiode (PD)-type CMOS active pixel sensor (APS) pixel is comprised of a reverse-biased p-n-junction diode (PD) for photon conversion and charge storage, and a number of MOS transistors. Junction capacitance of the PD has two major components; bottom plate (area) and side wall (periphery). Both play important roles in the electro-optical performance of PD-APS pixels. This paper reports PD peripheral junction utilization effects on the pixel's electro-optical performance, full-well capacity and spectral response for an 18times 18 mum CMOS PD-APS pixel were improved by opening multiple circular holes in the PD diffusion layer. A prototype CMOS APS imager was designed, fabricated, and tested in 0.5-mum, 5 V, 2P3M CMOS process, containing a 424 times 424 pixel array with smaller sub-arrays for multiple pixel designs. Four test pixels with 7, 11, 14, and 17 circular, 1.6-mum-diameter holes were placed on one pixel array, with one control pixel for reference. Pixel characteristics, dark current, PD capacitance, quantum efficiency, sensitivity, and pixel full-well capacity were measured. It was found that increased PD junction peripheral would potentially help to improve total capacitance of the PD, with the expense of higher dark current. We also found that increased PD peripheral capacitance improves spectral response up to 12% of the PD-APS pixel, especially at short wavelengths. View full abstract»

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  • Power and Area-Efficient Adaptive Equalization at Microwave Frequencies

    Publication Year: 2008 , Page(s): 1412 - 1420
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (867 KB) |  | HTML iconHTML  

    We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the lumped parameter equalizer, addresses several of the problems associated with conventional microwave equalizers based on the tapped delay line structure. The theory is given, and simulation results comparing it with the performance of ideal tapped delay line filters are shown. Circuit implementations are discussed, along with the effect of nonidealities on equalizer performance. View full abstract»

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  • On the Evaluation of the Exact Output of a Switched Continuous-Time Filter and Applications

    Publication Year: 2008 , Page(s): 1421 - 1429
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    In this paper, a study of the operation of switched continuous-time filters (SCTFs), defined as continuous-time filters with elements that are alternatively switched on and off in the signal path, is conducted. A well-known example is the use of switched resistors to multiply their value, but the universe of applications is wider. First, a detailed calculation of the output of an SCTF in the frequency domain, which allows the examination of any SCTF in a general framework, is presented. This result particularly explains the resistor multiplication effect. Three application examples using switched elements are presented and examined as SCTFs: a nonideal sample & hold, a switched active filter that is tuned by varying the duty cycle of the switching, and a switched Gm-C filter to implement a chopper amplifier. In all cases, the theoretical background allows the examination of circuit behavior and limitations, and the analysis is supported by measurements or transient simulations. View full abstract»

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  • An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

    Publication Year: 2008 , Page(s): 1430 - 1440
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (986 KB) |  | HTML iconHTML  

    This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-mum CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively. View full abstract»

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  • Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

    Publication Year: 2008 , Page(s): 1441 - 1454
    Cited by:  Papers (57)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1188 KB) |  | HTML iconHTML  

    The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies. View full abstract»

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  • A Heterogeneous 16-Bit DAC Using a Replica Compensation

    Publication Year: 2008 , Page(s): 1455 - 1463
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1203 KB) |  | HTML iconHTML  

    A highly monotonic very low power 16-bit 2-MS/s digital-to-analog converter (DAC) for high-resolution control loop systems is proposed and demonstrated. Replica compensation is used in improving the monotonicity of a heterogeneous DAC composed of a coarse current steering DAC and a fine resistor-ladder DAC. A complete DAC, including an on-chip bandgap reference and an output buffer, consumes only 0.6 mA with a 2.7-V supply. The 2.19-mm2 DAC with 10-I/O bonding pads implemented in 0.18-mum Bi-CMOS process achieves plusmn0.8 least significant bit (LSB) differential nonlinearity, plusmn4 LSB integral nonlinearity, and plusmn3-mV offset error at 2-MS/s sample rate. View full abstract»

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  • A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications

    Publication Year: 2008 , Page(s): 1464 - 1477
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3477 KB) |  | HTML iconHTML  

    In the fields of wireless bioelectronics implants and sensor network systems, amplitude shift keying (ASK) is one of the most commonly used schemes employed to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. It features the abilities of working on a very small modulation index and being provided without any R/C component(s) inside by means of a self-sampling scheme. The design has been implemented in an 18-mum CMOS process. The demodulator circuit occupies a die size of merely 32.3 times 14.5 mu m2. Analytic results from both simulated gradation and fabricated chips show that the proposed circuit can operate at a carrier of 2 MHz and achieve a modulation rate of up to 50%. The results also demonstrate that the presented work can still perform a proper demodulation even with a modulation index beneath 5.5%. An average power of approximately 336 muW was confirmed in return for the remarkable advantages. All aspects regarding the design, including a review of the prior arts, system consideration, circuit description, and analyses from simulation phase to actual measurement, are presented in detail. View full abstract»

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  • A Novel BPSK Demodulator for Biological Implants

    Publication Year: 2008 , Page(s): 1478 - 1484
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1295 KB) |  | HTML iconHTML  

    A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector based phase-locked loop allowing for robust performance compared to prior art. Two different circuit implementations for the novel demodulator architecture are proposed. Based on theoretical analysis, the maximum data rate of the demodulator is derived to be 1/8th of the carrier frequency. For experimental validation, a prototype was implemented for a 13.56-MHz BPSK demodulator in a 0.5-mum CMOS technology. The circuit occupies 1 mm2 chip area and consumes 3-mW power without any circuit optimization and can be further improved. Bit-error rate measurements have also been presented for a 20-kbs data rate. View full abstract»

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  • Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

    Publication Year: 2008 , Page(s): 1485 - 1494
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture. View full abstract»

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  • Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

    Publication Year: 2008 , Page(s): 1495 - 1501
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1490 KB) |  | HTML iconHTML  

    This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 27 -1, 210 -1, 215 -1, 2 23 -1, and 231 -1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-mum CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators. View full abstract»

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  • Fast Sign Detection for RNS (2^{n}-1,2^{n},2^{n}+1)

    Publication Year: 2008 , Page(s): 1502 - 1511
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    In this paper, we propose a fast algorithm for sign-extraction of a number given in the Residue Number System (2n-1,2n,2n+1) . The algorithm can be implemented using three n-bit wide additions, two of which can be done in parallel. It can be used in a wide variety of problems, i.e., in algorithms for dividing numbers in the RNS, or in evaluating the sign of determinant in computational geometry, etc. View full abstract»

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  • Robust Optical Time-of-Flight Range Imaging Based on Smart Pixel Structures

    Publication Year: 2008 , Page(s): 1512 - 1525
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1047 KB) |  | HTML iconHTML  

    The reliable detection of the three-dimensional position of arbitrary objects in a scene is a key capability of most animals and one of the most important tasks in machine vision. Today's preferred technical solution is optical time-of-flight (TOF) range imaging, due to its simplicity, its distance resolution, its large and adaptable measurement range, as well as the absence of shadowing problems. In order significantly to extend the application areas of TOF 3-D cameras, in particular for outdoor use, we show how their performance can be improved in all relevant respects: background light suppression is improved by an order of magnitude by the minimum charge transfer method. Multicamera operation is achieved by a binary pseudo-noise modulation/demodulation technique. This method also avoids all practical ambiguity problems typically encountered with harmonic modulation. Higher temporal demodulation resolution becomes possible with a pixel structure employing lateral electric fields. We have realized such pixels with a commercially available CCD/CMOS process, and our measurement results confirm that gigahertz demodulation imaging is possible. The practicality of all theoretical concepts is demonstrated with a miniaturized TOF 3-D camera platform whose LED array light source is modulated at a typical rate of 20 MHz. Our work contributes, therefore, to opening up new application domains of the soaring optical TOF range imaging techniques. View full abstract»

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  • A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video

    Publication Year: 2008 , Page(s): 1526 - 1535
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1185 KB) |  | HTML iconHTML  

    Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with plusmn128 search range within just 256 cycles, 5.95-KB buffers, and 213.7 K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-mum process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design. View full abstract»

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  • An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

    Publication Year: 2008 , Page(s): 1536 - 1545
    Cited by:  Papers (30)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined by finding the boundary values of the coefficient using linear programming. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware-efficient filters. The superiority of the algorithm on existing methods in terms of SPT term count, design time, hardware complexity, and power performance is shown with several design examples. Up to 30% reduction in the number of SPT terms is achieved over unoptimized Remez coefficients, which is 20% better than compared optimization methods. The average power saving is 20% over unoptimized coefficients, which is up to 14% better than optimized coefficients obtained with existing methods. View full abstract»

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  • A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

    Publication Year: 2008 , Page(s): 1546 - 1559
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1494 KB) |  | HTML iconHTML  

    A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer function. The systolic array enables real-time implementation of 3-D IIR frequency-planar filters at radio-frequency (RF) frame-rates and is therefore a suitable building block for 3-D IIR digital filters having beam- and cone-shaped passbands as required for smart-antenna-array beam-forming applications involving the broadband spatio-temporal filtering of plane-waves. The fixed-point systolic-array implementation have a throughput of OFPCC and the tested real-time prototype achieves frame (clock) sample frequencies of up to 90 MHz using one Xilinx Virtex-4 sx35-10ff668 FPGA device. View full abstract»

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  • Optimal Design of Frequency-Response Masking Filters With Reduced Group Delays

    Publication Year: 2008 , Page(s): 1560 - 1570
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    In this paper, a new method for the design of optimal finite-impulse response frequency-response masking (FRM) filters with reduced passband group delays is proposed. To meet the prescribed magnitude response and group delay, the proposed design method takes into account both the magnitude error and the group delay error. The key step is the derivation of the group delay and its gradient with respect to the filter coefficients, based on which an explicit group delay constraint is formulated. By incorporating the group delay constraint into the overall optimization, FRM filters with better approximation to the prescribed reduced group delay can be obtained in comparison with a method by Lu and Hinamoto in 2003, as illustrated by two design examples. View full abstract»

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  • Blind-Channel Identification for MIMO Single-Carrier Zero-Padding Block-Transmission Systems

    Publication Year: 2008 , Page(s): 1571 - 1579
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (691 KB) |  | HTML iconHTML  

    We propose a blind identification method for multiple-input multiple-output (MIMO) single-carrier zero-padding block-transmission systems. The method uses periodic precoding on the source signal before transmission. The estimation of the channel impulse response matrix consists of two steps: 1) obtain the channel product matrix by solving a lower-triangular linear system; 2) obtain the channel impulse response matrix by computing the positive eigenvalues and eigenvectors of a Hermitian matrix formed from the channel product matrix. The method is applicable to MIMO channels with more transmitters or more receivers. A sufficient condition for identifiability is simply that the channel impulse response matrix is full column rank. The design of the precoding sequence which minimizes the noise effect in covariance matrix estimation is proposed and the effect of the optimal precoding sequence on channel equalization is discussed. Simulations are used to demonstrate the performance of the method. View full abstract»

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  • ETHFB: A New Class of Even-Length Biorthogonal Wavelet Filters for Hilbert Pair Design

    Publication Year: 2008 , Page(s): 1580 - 1588
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    A new class of biorthogonal filter banks, called the even-triplet-halfband-filter-bank (ETHFB), is introduced here. The filters are of even length and have linear phase response. There are two versions of the ETHFB, and they are modifications of the (odd-length) triplet-halfband-filter-bank. The parametric Bernstein polynomial is utilized in the construction of the three kernels that define the ETHFB. These filters will be used to match a given odd-length filter bank such that the equivalent wavelet functions of both filter banks are approximate Hilbert transform of each other, i.e., a Hilbert pair. The determination of the design parameters of the filter bank is achieved through an efficient least-squares method. View full abstract»

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  • A Generalized Reverse Block Jacket Transform

    Publication Year: 2008 , Page(s): 1589 - 1600
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB) |  | HTML iconHTML  

    Jacket matrices motivated by the center weight Hadamard matrices have played important roles in signal processing, communication, image compression, cryptography, etc. In this paper we propose a notation called block Jacket matrix which substitutes elements of the matrix into common matrices or even block matrices. Employing the well-known Pauli matrices which are very important in many subjects, block Jacket matrices with any size are investigated in detail, and some recursive relations for fast construction of the block Jacket matrices are obtained. Based on the general recursive relations, several special block Jacket matrices are constructed. To decompose high order block Jacket matrices, a fast decomposition algorithm for the factorable block Jacket matrices is suggested. After that some properties of the block Jacket matrices are investigated. Finally, several remarks are presented. These remarks are associated with comparisons between the Clifford algebra and the block Jacket matrices, generations of orthogonal and quasi-orthogonal sequences, and relations of the block Jacket matrices to the orthogonal transforms for signal processing. Since the Pauli matrices are actually infinitesimal generators of SU(2) group, the proposed construction and decomposition algorithms for the block Jacket matrices are available in the signal processing, communication, quantum signal processing and information theory. View full abstract»

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  • An Unconstrained Architecture for Systematic Design of Higher Order \Sigma \Delta Force-Feedback Loops

    Publication Year: 2008 , Page(s): 1601 - 1614
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1313 KB) |  | HTML iconHTML  

    Nowadays, SigmaDelta-modulation is a widely used technique for analog-to-digital (A/D) conversion, especially when aiming for high resolutions. While being applied initially for purely electrical A/D converters, its application has been expanded to mixed mechanical-electrical systems. This has led to the use of SigmaDelta force-feedback for digital readout of high-performance inertial sensors. However, compared with their electrical counterpoint, SigmaDelta force-feedback loops often have to deal with three additional issues: 1) an increased stability problem due to phase-lag occurring in the sensor; 2) the injection of relatively high levels of readout noise in the loop; and 3) the lack of degrees-of-freedom of many SigmaDelta force-feedback architectures for implementing an arbitrary noise transfer function. As a result, SigmaDelta force-feedback loops found in literature are designed in a much less systematic way as compared with electrical SigmaDelta modulators. In this paper, we address these issues and propose a new unconstrained architecture. Based on this architecture, we are able to present a systematic approach for designing SigmaDelta force-feedback loops. Additionally, the main strengths and weaknesses of different SigmaDelta force-feedback architectures are discussed. View full abstract»

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  • Algorithmic ADC Offset Compensation by Nonwhite Data Chopping: System Model and Basic Theoretical Results

    Publication Year: 2008 , Page(s): 1615 - 1627
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (858 KB) |  | HTML iconHTML  

    This paper is devoted to show the impact of nonwhite chopping on the offset compensation in time-interleaved analog-to-digital converters. We develop a theoretical framework allowing the selection of optimal chopping sequences. We show that, on the one hand, the adoption of these (generally nonwhite) sequences allows to achieve faster offset compensation (thus increasing the signal-to-noise ratio) and, on the other hand, a better spectral shaping (thus increasing the spurious-free dynamic range). As a byproduct of our analysis, we prove that the average offset estimation which is used in many ADC implementations is asymptotically the best available linear estimation of offset that, in turn, is the best estimation when the signal to be converted can be assumed to be a Gaussian process. View full abstract»

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  • Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs

    Publication Year: 2008 , Page(s): 1628 - 1638
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1347 KB) |  | HTML iconHTML  

    This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. To show the flexibility of this approach, many case studies are reported; among them, the analysis of the spurs due to charge pump mismatch and the transient phase noise, and spurs performances of a PLL featuring a dual control of the voltage-controlled oscillator. View full abstract»

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  • A Spur Elimination Technique for Phase Interpolation-Based Fractional- N PLLs

    Publication Year: 2008 , Page(s): 1639 - 1647
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-N phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional-N PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras