# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2008, Page(s): C2
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• ### Guest Editorial—ISCAS 2007

Publication Year: 2008, Page(s):713 - 714
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• ### Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

Publication Year: 2008, Page(s):715 - 721
Cited by:  Papers (23)
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This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moder... View full abstract»

• ### Process/Temperature Variation Tolerant Precision Signal Strength Indicator

Publication Year: 2008, Page(s):722 - 729
Cited by:  Papers (16)
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A receiving signal strength indicator (RSSI) built with transconductance amplifiers is presented. The RSSI achieves high tolerance to process/temperature variations by utilizing the unique nature of branch currents in a transconductance amplifier. These branch currents are used to implement a current-mode rectifier and amplitude clipping circuit that are tolerant of process variations. An on-chip ... View full abstract»

• ### A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

Publication Year: 2008, Page(s):730 - 740
Cited by:  Papers (12)  |  Patents (1)
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This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area... View full abstract»

• ### Cascaded Diophantine Frequency Synthesis

Publication Year: 2008, Page(s):741 - 751
Cited by:  Papers (7)
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Cascaded diophantine frequency synthesis (CDFS) is an approach to high-resolution frequency synthesis based on the mathematical properties of integer numbers and diophantine equations. CDFS can be implemented using two or more phase-locked loops (PLLs) and frequency mixing stages in a cascade topology. CDFS achieves frequency resolution arbitrarily finer than that of the constituent PLLs while mai... View full abstract»

• ### Desensitized CMOS Low-Noise Amplifiers

Publication Year: 2008, Page(s):752 - 765
Cited by:  Papers (9)
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The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, Rn, significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. ... View full abstract»

• ### Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop

Publication Year: 2008, Page(s):766 - 774
Cited by:  Papers (18)
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This paper presents a new algorithm and circuit implementation for high-speed frequency-to-voltage converters (FVC). The proposed system overcomes the deficiencies of a previously reported converter and can operate about 20 times faster. To validate this FVC and show its usefulness, it was used in the design of a frequency locked loop. For the design of this loop, it was found that existing analyt... View full abstract»

• ### Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

Publication Year: 2008, Page(s):775 - 785
Cited by:  Papers (21)
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A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fmax are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper sele... View full abstract»

• ### A bandpass filter with inherent gain adaptation for hearing applications

Publication Year: 2008, Page(s):786 - 795
Cited by:  Papers (14)
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In this paper, we propose a novel bandpass filter design that incorporates automatic gain control (AGC). The gain control in the filter reduces the performance requirements of a wide-band AGC, and allows for low-power multichannel compression. The filter achieves up to 15 dB of compression on a 55-dB input dynamic range and is tunable over the audio frequency range, with microwatt power consumptio... View full abstract»

• ### A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

Publication Year: 2008, Page(s):796 - 803
Cited by:  Papers (12)  |  Patents (1)
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This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting t... View full abstract»

• ### A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

Publication Year: 2008, Page(s):804 - 816
Cited by:  Papers (9)
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In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without an... View full abstract»

• ### Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

Publication Year: 2008, Page(s):817 - 827
Cited by:  Papers (8)
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A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-... View full abstract»

• ### Arithmetic Unit for Finite Field ${rm GF}(2^{m})$

Publication Year: 2008, Page(s):828 - 837
Cited by:  Papers (7)
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An arithmetic unit (AU) that performs all basic arithmetic operations in the finite field GF(2m) is presented, where m is an arbitrary integer. The presented finite field AU consists of an arithmetic processor, an arithmetic logic unit, and a control unit. The proposed AU has low circuit complexity and is programmable, so that any error-correcting decoder that operates in GF(2m View full abstract»

• ### Beamforming of Broad-Band Bandpass Plane Waves Using Polyphase 2-D FIR Trapezoidal Filters

Publication Year: 2008, Page(s):838 - 850
Cited by:  Papers (16)
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A new discrete-domain method is proposed for the beamforming of temporally broad-band bandpass plane waves (PWs) using a real-coefficient 2-D spatio-temporal (ST) finite-impulse response (FIR) filter having a novel rectangularly symmetric double-trapezoidal-shaped passband. The arriving temporally broad-band-bandpass ST PWs are received by a 1-D uniformly distributed sensor array. The sensor signa... View full abstract»

• ### Perfect Blind-Channel Shortening for Multicarrier Systems

Publication Year: 2008, Page(s):851 - 860
Cited by:  Papers (6)
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In multicarrier systems, when the order of a channel impulse response is larger than the length of the cyclic prefix (CP), there is a significant performance degradation due to interblock interference (IBI). This paper proposes a blind-channel shortening method in which the equalizer parameter vector is formed by the noise subspace of the received signal correlation matrix so that the output power... View full abstract»

• ### Fully Digital Random Bit Generators for Cryptographic Applications

Publication Year: 2008, Page(s):861 - 875
Cited by:  Papers (15)  |  Patents (2)
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This paper is devoted to the analysis, implementation, and modeling of fully digital random bit generators based on recent research results on the design of stateless oscillator-based generators. A new approach to the data quality test is adopted where, instead of passing bunches of statistical tests on the raw data, the focus is on the verification of a minimum entropy limit for the delive... View full abstract»

• ### Phase-Shift-Free $M$-Phase Spreading Sequences of Markov Chains

Publication Year: 2008, Page(s):876 - 882
Cited by:  Papers (3)
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We consider the optimum spreading sequences of Markov chains in terms of the mean value of the limit of variance of the normalized multiple-access interference for asynchronous spread-spectrum multiple access communication systems. We first define a novel class of spreading sequences, namely the phase-shift-free M(ges 3)-phase spreading sequences. Then we theoretically and experimentally show that... View full abstract»

• ### Chaotic Synchronization Using Sampled-Data Fuzzy Controller Based on Fuzzy-Model-Based Approach

Publication Year: 2008, Page(s):883 - 892
Cited by:  Papers (28)
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This paper presents the synchronization of chaotic system using a sampled-data fuzzy controller. To carry out the system analysis, a fuzzy model is employed to represent the chaotic systems. Linear-matrix-inequality (LMI)-based system stability and performance conditions are derived using a Lyapunov-based approach. The derived LMI-based stability and performance conditions are employed to aid the ... View full abstract»

• ### Synchronization of Chaotic Systems Using Time-Delayed Fuzzy State-Feedback Controller

Publication Year: 2008, Page(s):893 - 903
Cited by:  Papers (29)
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This paper presents the fuzzy-model-based control approach to synchronize two chaotic systems subject to parameter uncertainties. A fuzzy state-feedback controller using the system state of response chaotic system and the time-delayed system state of drive chaotic system is employed to realize the synchronization. The time delay which complicates the system dynamics makes the analysis difficult. T... View full abstract»

• ### Template Design for Cellular Nonlinear Networks With 1-Bit Weights

Publication Year: 2008, Page(s):904 - 913
Cited by:  Papers (12)
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In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithmically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as ... View full abstract»

• ### On-Chip Power-Grid Simulation Using Latency Insertion Method

Publication Year: 2008, Page(s):914 - 931
Cited by:  Papers (51)
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Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion me... View full abstract»

• ### Control of a planar system with quantized and saturated input/output

Publication Year: 2008, Page(s):932 - 942
Cited by:  Papers (19)
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The stabilization problem for a simple (unstable) planar system in the presence of input and output quantization and saturation is addressed. It is shown that global stability to a terminal set, the size of which can be arbitrarily reduced, is achieved by means of a hybrid output feedback control law, which reads out the plant only three values and delivers a control action composed of three value... View full abstract»

• ### Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems

Publication Year: 2008, Page(s):943 - 952
Cited by:  Papers (8)
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This work presents a novel carrier frequency offset (CFO) estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the conditions of I/Q mismatch for direct conversion structures with 2-dB gain error and 20-deg. phase error in frequency selective fading channels. To circumvent CFO with I/Q mismatch, the proposed P-CFO algorithm rotates three training symbols by adding ext... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK