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Circuits and Systems for Video Technology, IEEE Transactions on

Issue 4 • Date Dec 1992

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Displaying Results 1 - 7 of 7
  • A VLSI chip set for high-speed lossless data compression

    Publication Year: 1992 , Page(s): 381 - 391
    Cited by:  Papers (15)  |  Patents (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB)  

    A VLSI implementation of a lossless data compression algorithm is reported. This is the first implementation of an encoder/decoder chip set that uses the Rice (see JPL Publication 91-1, 1991) algorithm and provides an introduction to the algorithm and a description of the high-performance hardware. The algorithm is adaptive over a aide entropy range. Its performance on several 8-b test images exceeds other techniques employing differential pulse code modulation (DPCM) followed by arithmetic coding, adaptive Huffman coding, and a Lempel-Ziv-Welch (LZW) algorithm. A major feature of the algorithm is that it requires no look-up tables or external RAM. There are only 71000 transistors required to implement the encoder and decoder. Each chip was fabricated in a 1.0-μm CMOS process and both are only 5 mm on a side. A comparison is made with other hardware realizations. Under laboratory conditions, the encoder compresses at a rate in excess of 50 Msamples/s and the decoder operates at 25 Msamples/s. The current implementation processes quantized data from 4 to 14 b/sample View full abstract»

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  • Switched capacitor networks for focal plane image processing systems

    Publication Year: 1992 , Page(s): 392 - 400
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    The use of switched capacitor (SC) networks as an alternative to large resistor networks for performing computations in VLSI circuits for real-time machine vision and image processing systems is investigated. A mapping can be made from any resistor network to an equivalent SC network that has the same node voltage solution in steady state. However, it takes several switching cycles for a charge to be distributed in the SC network before steady state is reached. Results indicate that SC networks can be used in moderate resolution systems (250×250 pixels) operating at video rate. A chip that implemented several switched capacitor networks for spatial smoothing of images in one dimension was fabricated and tested. The amount of spatial smoothing can be adjusted when the clocking scheme applied to the network is varied View full abstract»

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  • Constraints on variable bit-rate video for ATM networks

    Publication Year: 1992 , Page(s): 361 - 372
    Cited by:  Papers (101)  |  Patents (52)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB)  

    Constraints on the encoded bit rate of a video signal that are imposed by a channel and encoder and decoder buffers are considered. Conditions that ensure that the video encoder and decoder buffers do not overflow or underflow when the channel can transmit a variable bit rate are presented. Using these conditions and a commonly proposed network-user contract, the effect of a (BISDN) network policing function on the allowable variability in the encoded video bit rate is examined. It is shown how these ideas might be implemented in a system that controls both the encoded and transmitted bit rates. The performance of video that has been encoded using the derived constraints for the leaky bucket channel is presented View full abstract»

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  • Design and implementation of multidimensional Y-C separation filters for NTSC signals

    Publication Year: 1992 , Page(s): 373 - 380
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    A design method for three-dimensional Y-C separation filters for the NTSC signals is proposed. The 3-D spectral structure of the NTSC signals, together with some existing and previously proposed Y-C separation methods, are first reviewed to point out some drawbacks in these methods. Since the proposed Y-C separation filter consists of a horizontal one-dimensional FIR filter and a temporal-vertical two-dimensional nonseparable FIR filter, the design of the 2-D filter, which is more difficult to design than the 1-D one, is considered more fully. The design procedure is simplified by applying some 2-D frequency transformations and then formulated as a simple linear programming problem, which can be solved easily by the standard method (e.g., the revised simplex method). Another advantage of the approach is the flexibility as regards to the shape of the passband and the support of the impulse response. Two design examples are given and a hardware implementation is considered View full abstract»

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  • DCT-based codebook design for vector quantization of images

    Publication Year: 1992 , Page(s): 401 - 409
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    A codebook design algorithm based on a two-dimensional discrete cosine transform (2-D DCT) is presented for vector quantization (VQ) of images. The significant features of training images are extracted by using the 2-D DCT. A codebook is generated by partitioning the training set into a binary tree. Each training vector at a nonterminal node of the binary tree is directed to one of the two descendants by comparing a single feature associated with that node to a threshold. Compared with the pairwise nearest neighbor (PNN) algorithm, the algorithm results in a considerable reduction in computation time and shows better picture quality View full abstract»

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  • Nonstationary AR modeling and constrained recursive estimation of the displacement field

    Publication Year: 1992 , Page(s): 334 - 346
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1668 KB)  

    An approach to constrained recursive estimation of the displacement vector field (DVF) in image sequences is presented. An estimate of the displacement vector at the working point is obtained by minimizing the linearized displaced frame difference based on a set of observations that belong to a causal neighborhood (mask). An expression for the variance of the linearization error (noise) is obtained. Because the estimation of the DVF is an ill-posed problem, the solution is constrained by considering an autoregressive (AR) model for the DVF. A nonstationary AR model of the DVF is also considered. Additional information about the solution is incorporated into the algorithm using a causal oriented smoothness constraint. A set theoretic regularization approach based on this formulation results in a weighted constrained least-squares estimation of the DVF. The algorithm shows an improved performance with respect to accuracy, robustness of occlusion, and smoothness of the estimated DVF when applied to typical videoconferencing scenes View full abstract»

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  • High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

    Publication Year: 1992 , Page(s): 347 - 360
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1316 KB)  

    The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance View full abstract»

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Aims & Scope

The emphasis is focused on, but not limited to:
1. Video A/D and D/ A
2. Video Compression Techniques and Signal Processing
3. Multi-Dimensional Filters and Transforms
4. High Speed Real-Tune Circuits
5. Multi-Processors Systems—Hardware and Software
6. VLSI Architecture and Implementation for Video Technology 

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dan Schonfeld
Multimedia Communications Laboratory
ECE Dept. (M/C 154)
University of Illinois at Chicago (UIC)
Chicago, IL 60607-7053
tcsvt-eic@tcad.polito.it

Managing Editor
Jaqueline Zelkowitz
tcsvt@tcad.polito.it