# IEEE Transactions on Circuits and Systems I: Regular Papers

### Early Access Articles

Early Access articles are made available in advance of the final electronic or print versions. Early Access articles are peer reviewed but may not be fully edited. They are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 125
• ### Fault Detection for Linear Discrete Time-Varying Systems With Multiplicative Noise: The Finite-Horizon Case

Publication Year: 2018, Page(s):1 - 14
| | PDF (1544 KB)

This paper studies the problem of fault detection for linear discrete time-varying systems with multiplicative noise in finite-horizon, where our main object is to provide an optimal fault detection filter (FDF) design scheme such that stochastic sensitivity/robustness ratio for fault diagnosis is maximized in the sense of probability 1. An operator-aided optimization approach and a generalized FD... View full abstract»

• ### A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

Publication Year: 2018, Page(s):1 - 11
| | PDF (2548 KB)

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5-μm CMOS process, is proposed in this paper. The BGR utilizes successive voltage-step compensation to produce a temperature-insensitive voltage reference (VR), including one ΔVGS step for first-order compensation and another one for higher order curvature correction. Moreover, a supply noise bypa... View full abstract»

• ### Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories

Publication Year: 2018, Page(s):1 - 11
| | PDF (2696 KB)

This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no... View full abstract»

• ### Data-Driven Filtering for Nonlinear Systems With Bounded Noises and Quantized Measurements

Publication Year: 2018, Page(s):1 - 10
| | PDF (1694 KB)

This paper focuses on the data-driven filtering problem on nonlinear systems with bounded noises and quantized measurements which are subject to logarithmic quantization. Because the accurate system model is unknown, an almost-optimal data-driven filter is designed from an available data set within the nonlinear set membership framework. The set is composed of system inputs and quantized measureme... View full abstract»

• ### Event-Based Consensus for a Class of Nonlinear Multi-Agent Systems With Sequentially Connected Topology

Publication Year: 2018, Page(s):1 - 13
| | PDF (2069 KB)

To reduce actuation burden in dynamical network environment, the event-triggering strategy is applied to consensus protocol for a class of nonlinear multi-agent systems with a switching topology. The considered switching topology is assumed to be sequentially connected, which is directed disconnected. The combinational measurement approach is adopted in the event-triggering strategy such that each... View full abstract»

• ### A Simple Piecewise Model of Reset/Set Transitions in Bipolar ReRAM Memristive Devices

Publication Year: 2018, Page(s):1 - 12
| | PDF (3065 KB)

In this paper, we develop and test a piecewise model for the reset and set transitions of a bipolar ReRAM memristive device in the flux-charge space, instead of the usual voltage-current one. To do so, we consider the devices as memristors. The model used is very simple and provides accurate simulation results. It also allows the development of simple expressions for the conductance and power cons... View full abstract»

• ### An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

Publication Year: 2018, Page(s):1 - 9
| | PDF (2500 KB)

Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-2² multiple delay commutator architecture utilizing the advantages of the radix-2² algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher thro... View full abstract»

• ### A K-/Ka-Band Concurrent Dual-Band Single-Ended Input to Differential Output Low-Noise Amplifier Employing a Novel Transformer Feedback Dual-Band Load

Publication Year: 2018, Page(s):1 - 12
| | PDF (3863 KB)

A concurrent dual-band single-ended input to differential output (single-ended-to-differential) low-noise amplifier (LNA) employing a novel transformer feedback single-ended-to-differential dual-band load is proposed. The developed LNA topology is flexible in controlling the stopband notch frequency by optimizing the transformer's self-inductance and coupling coefficient. It also has a unique adva... View full abstract»

• ### Finite-Time H∞ State Estimation for Discrete Time-Delayed Genetic Regulatory Networks Under Stochastic Communication Protocols

Publication Year: 2018, Page(s): 1
| | PDF (1094 KB)

This paper investigates the problem of finite-time H∞ state estimation for discrete time-delayed genetic regulatory networks under stochastic communication protocols (SCPs). The network measurements are transmitted from two groups of sensors to a remote state estimator via two independent communication channels of limited bandwidths, and two SCPs are utilized to orchestrate the transmission... View full abstract»

• ### Time-Domain Characterization of Digitized PWM Inverter With Dead-Time Effect

Publication Year: 2018, Page(s):1 - 10
| | PDF (6519 KB)

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling... View full abstract»

• ### ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity

Publication Year: 2018, Page(s):1 - 12
| | PDF (4804 KB)

Computationally-secure cryptographic algorithms implemented on a physical platform leak significant side-channel' information through their power supplies. Correlational power attack is an efficient power side-channel attack (SCA) technique, which analyzes the statistical correlation between the estimated and the measured supply current traces to extract the secret key. The existing power SCA co... View full abstract»

• ### A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications

Publication Year: 2018, Page(s):1 - 11
| | PDF (3649 KB)

This paper reports a wideband inductorless automatic gain control (AGC) amplifier for wireline applications. To realize a dB-linear AGC range, a pseudo-folded Gilbert cell driven by a single-branch negative exponential generator (NEG) is proposed as the core variable-gain amplifier. The NEG features a composite of dual Taylor series to extend the AGC approximation range without sacrificing the pre... View full abstract»

• ### Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator

Publication Year: 2018, Page(s):1 - 10
| | PDF (2261 KB)

Shielding, which is used in VLSI designs to prevent noise interference from the cross-coupling capacitance between adjacent signals can also be used to tune the propagation delay of the clock signals in designs operating at low GHz frequencies. This paper presents a detailed design for a 16-nm ring oscillator with built-in reconfigurable shielding, and a delay estimation methodology. Together thes... View full abstract»

• ### Random Fourier Filters Under Maximum Correntropy Criterion

Publication Year: 2018, Page(s):1 - 14
| | PDF (2852 KB)

Random Fourier adaptive filters (RFAFs) project the original data into a high-dimensional random Fourier feature space (RFFS) such that the network structure of filters is fixed while achieving similar performance with kernel adaptive filters. The commonly used error criterion in RFAFs is the well-known minimum mean-square error (MMSE) criterion, which is optimal only under the Gaussian noise assu... View full abstract»

• ### Resilient Filtering for Linear Time-Varying Repetitive Processes Under Uniform Quantizations and Round-Robin Protocols

Publication Year: 2018, Page(s):1 - 13
| | PDF (2955 KB)

In this paper, the resilient filtering problem is investigated for a class of linear time-varying repetitive processes with communication constraints. The communication between the sensors and the remote filter, which is subject to uniform quantizations, is carried out through a shared communication medium where only one sensor has access to the network at each transmission time. To prevent data f... View full abstract»

• ### Finite Frequency Filtering Design for Uncertain Discrete-Time Systems Using Past Output Measurements

Publication Year: 2018, Page(s):1 - 9
| | PDF (1299 KB)

This paper tackles the problem of finite frequency H∞ filtering design for polytopic uncertain discrete-time systems using past output measurements. The noise is assumed to be restricted in a finite frequency range, i.e., the low, middle, or high frequency range. The objective is to design an admissible filter with past output measurements of the system, guaranteeing the asymptotic stabilit... View full abstract»

• ### Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time $ΔΣ$ Modulators

Publication Year: 2018, Page(s):1 - 11
| | PDF (1842 KB)

Chopping is a technique to reduce offset and flicker noise in amplifiers by up-converting them to higher frequency, and subsequently filtering them out. A typical chopping implementation uses two complementary phases which have a finite non-overlap time in between them. When such a chopping phase is used in the first integrator of a continuous-time delta sigma modulator, the non-overlap time can s... View full abstract»

• ### An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture

Publication Year: 2018, Page(s):1 - 12
| | PDF (2132 KB)

This paper presents an energy-efficient network-on-chip (NoC)-based multi-core architecture for realizing a reconfigurable Viterbi decoder (VD). The proposed architecture can support a wide range of wireless communication standards that have varied constraint lengths. The energy efficiency in the proposed architecture has been primarily achieved by mapping the add-compare-select operations of the ... View full abstract»

• ### Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's

Publication Year: 2018, Page(s):1 - 14
| | PDF (4011 KB)

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is sh... View full abstract»

• ### Process Scalability of Pulse-Based Circuits for Analog Image Convolution

Publication Year: 2018, Page(s):1 - 10
| | PDF (2175 KB)

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transisto... View full abstract»

• ### New Approach to Fixed-Order Output-Feedback Control for Piecewise-Affine Systems

Publication Year: 2018, Page(s):1 - 9
| | PDF (850 KB)

This paper studies the fixed-order piecewise-affine (PWA) output-feedback control of PWA systems in an H∞ setup. In particular, the conventional output-feedback closed-loop system is first augmented with the introduction of the input vector, and a descriptor presentation of PWA system is acquired. Then, a bounded real lemma is derived for the resulting PWA system, which is realized by the c... View full abstract»

• ### Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition

Publication Year: 2018, Page(s):1 - 13
| | PDF (9615 KB)

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and... View full abstract»

• ### Toward Stronger Robustness of Network Controllability: A Snapback Network Model

Publication Year: 2018, Page(s):1 - 9
| | PDF (2481 KB)

A new complex network model, called q-snapback network, is introduced. Basic topological characteristics of the network, such as degree distribution, average path length, clustering coefficient, and Pearson correlation coefficient, are evaluated. The typical 4-motifs of the network are simulated. The robustness of both state and structural controllabilities of the network against targeted and rand... View full abstract»

• ### Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC

Publication Year: 2018, Page(s):1 - 10
| | PDF (1906 KB)

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especial... View full abstract»

• ### Generating the Closed-Form Second-Order Characteristics of Analog Differential Cells by Symbolic Perturbation

Publication Year: 2018, Page(s):1 - 12
| | PDF (1202 KB)

Analog integrated circuit designers always use closed-form design equations in design reasoning. However, most of the time, they have to derive all equations by hand. When high-order effects are of interest, manual derivation would become much harder. Although the art of symbolic circuit analysis has been making steady progress, symbolically generating closed-form equations for high-order effect i... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK