# IEEE Transactions on Circuits and Systems I: Regular Papers

### Early Access Articles

Early Access articles are made available in advance of the final electronic or print versions. Early Access articles are peer reviewed but may not be fully edited. They are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 104
• ### ChipNet: Real-Time LiDAR Processing for Drivable Region Segmentation on an FPGA

Publication Year: 2018, Page(s):1 - 11
| | PDF (2541 KB)

This paper presents a field-programmable gate array (FPGA) design of a segmentation algorithm based on convolutional neural network (CNN) that can process light detection and ranging (LiDAR) data in real-time. For autonomous vehicles, drivable region segmentation is an essential step that sets up the static constraints for planning tasks. Traditional drivable region segmentation algorithms are mos... View full abstract»

• ### FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and Applications

Publication Year: 2018, Page(s):1 - 12
| | PDF (5096 KB)

Exploring the use of fractional calculus is essential for it to be used properly in various applications. Implementing the fractional operator $D^α$ in FPGA is an important research topic in fractional calculus; in the literature, only a few FPGA implementations have been proposed due to the memory dependence of the fractional order systems. In this paper, FPGA implementations of fractional order ... View full abstract»

• ### Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

Publication Year: 2018, Page(s):1 - 14
| | PDF (2758 KB)

This paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture using single read/single write port memory banks. The throughput of such an architecture is limited by memory access conflicts, due to improper message mapping in the memory ban... View full abstract»

• ### A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor

Publication Year: 2018, Page(s):1 - 10
| | PDF (2233 KB)

Lattice-based cryptography has shown great potential due to its resistance against quantum attacks. With the security requirements for high-precision Gaussian sampling and complex polynomial multiplication over rings, as well as storage of large public-keys, it is extremely challengeable but important to implement lattice-based schemes on resources constrained devices. In this paper, a resource-ef... View full abstract»

• ### Design of Sparse FIR Filters With Reduced Effective Length

Publication Year: 2018, Page(s):1 - 11
| | PDF (2013 KB)

In this paper, an exchange algorithm is proposed to design sparse linear phase finite impulse response (FIR) filters with reduced effective length. The sparse FIR filter design problem is formally an l₀-norm minimization problem. This original design problem is re-formulated by encoding the filter coefficients using a binary encoding vector, which represents the locations of the zero and non-zero ... View full abstract»

• ### Upper and Lower Bounds for the Maximum Number of Frequencies That Can Be Generated by a Class of Fractional Oscillators

Publication Year: 2018, Page(s):1 - 10
| | PDF (1212 KB)

This paper deals with investigating the maximum number of frequencies generated by an oscillator in the case that a half number of integrators in the conventional dynamic structure of this oscillator are replaced by fractional integrators with an identical order. First, an upper bound for the maximum number of frequencies, which can exist in a steady state response of the oscillator, with respect ... View full abstract»

• ### A Fully Flexible Circuit Implementation of Clique-Based Neural Networks in 65-nm CMOS

Publication Year: 2018, Page(s):1 - 12
| | PDF (4744 KB)

Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is only usable in a unique use case. Besides, the silicon area of hardwired circuits grows exponentiall... View full abstract»

• ### Nonlinear Dynamic Modeling and Analysis of Self-Oscillating H-Bridge Parallel Resonant Converter Under Zero Current Switching Control: Unveiling Coexistence of Attractors

Publication Year: 2018, Page(s):1 - 11
| | PDF (2828 KB)

This paper deals with the global dynamical analysis of an H-bridge parallel resonant converter under a zero current switching control. Due to the discontinuity of the vector field in this system, sliding dynamics may take place. Here, the sliding set is found to be an escaping region. Different tools are combined for studying the stability of oscillations of the system. The desired crossing limit ... View full abstract»

• ### A Second-Order Bandpass ΔΣ Time-to-Digital Converter With Negative Time-Mode Feedback

Publication Year: 2018, Page(s):1 - 14
| | PDF (5177 KB)

This paper presents an all-digital bandpass Δ Σ time-to-digital converter (BP)Δ ΣTDC) for IF data conversion. The proposed TDC is based on a second-order resonator implemented by a cascade of two time-mode lossless discrete integrators (LDI), and a digital-to-time converter (DTC) in a feedback loop. The DTC is based on a new topology of double-edge voltage-controlled delay unit. The proposed TDC a... View full abstract»

• ### Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model

Publication Year: 2018, Page(s):1 - 13
| | PDF (3465 KB)

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good spe... View full abstract»

• ### A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding

Publication Year: 2018, Page(s):1 - 10
| | PDF (3464 KB)

This paper presents a low-complexity chase (LCC) decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced ... View full abstract»

• ### Linearization of Active Downconversion Mixers at the IF Using Feedforward Cancellation

Publication Year: 2018, Page(s):1 - 12
| | PDF (2714 KB)

A feedforward linearization technique for third-order intermodulation (IM₃) distortion cancellation in active downconversion mixers is proposed in this paper. Low-frequency second-order intermodulation (IM₂) tones are created and multiplied with the mixer's output to generate low-frequency IM₃ replicas for cancellation. Implemented mostly at the IF band, this technique brings a third-order input i... View full abstract»

• ### On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

Publication Year: 2018, Page(s):1 - 12
| | PDF (58554 KB)

In this paper, we augment a trapezoidal Quantum Point Contact topology with top gates to form a butterfly Graphene Nanoribbon (GNR) structure and demonstrate that by adjusting its topology, its conductance map can mirror basic Boolean functions, thus one can use such structures instead of transistors to build carbon-based gates and circuits. We first identify by means of Design Space Exploration s... View full abstract»

• ### The Theory of Special Noise Invariants

Publication Year: 2018, Page(s):1 - 14
| | PDF (1300 KB)

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove t... View full abstract»

• ### Efficient FPGA Implementations of Pair and Triplet-Based STDP for Neuromorphic Architectures

Publication Year: 2018, Page(s):1 - 13
| | PDF (3522 KB)

Synaptic plasticity is envisioned to bring about learning and memory in the brain. Various plasticity rules have been proposed, among which spike-timing-dependent plasticity (STDP) has gained the highest interest across various neural disciplines, including neuromorphic engineering. Here, we propose highly efficient digital implementations of pair-based STDP (PSTDP) and triplet-based STDP (TSTDP) ... View full abstract»

• ### A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation

Publication Year: 2018, Page(s):1 - 11
| | PDF (3026 KB)

This paper presents the theoretical and experimental results on the phase noise spectrum and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency-modulated continuous-wave (FMCW) chirp generation. The phase noise spectrum under modulation is analytically calculated for a second-order charge pump PLL with a feedback divider ratio linearly changing over time. This is fol... View full abstract»

• ### Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Publication Year: 2018, Page(s):1 - 13
| | PDF (2716 KB)

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interfere... View full abstract»

• ### New Mixed-Mode Design Methodology for High-Efficiency Outphasing Chireix Amplifiers

Publication Year: 2018, Page(s):1 - 14
| | PDF (5474 KB)

A new design methodology providing optimal mixed-mode operation for dual-input class-F outphasing Chireix amplifiers is presented. The design starts with single-transistor class-F simulations at the intrinsic I-V reference planes to directly select the optimal peak and backoff resistive loads Rmin and Rmax and input RF gate drives yielding the best combination of efficiencies and output powers wit... View full abstract»

• ### A Programmable Sustaining Amplifier for Flexible Multimode MEMS-Referenced Oscillators

Publication Year: 2018, Page(s):1 - 14
| | PDF (5093 KB)

This paper presents a programmable single-chip sustaining amplifier for MEMS-referenced oscillators. The chip integrates a low-noise amplifier, variable-gain amplifiers (VGAs), band-pass filters (BPFs), all-pass filters (APFs), automatic level control, and output buffers. It also contains a second signal path for background cancellation, i.e., eliminating the effect of electrical feedthrough capac... View full abstract»

• ### Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

Publication Year: 2018, Page(s):1 - 14
| | PDF (4038 KB)

This paper presents an energy- and area-efficient architecture for approximated discrete cosine transform (DCT). Due to the good compression ability, DCT is widely exploited in signal processing. However, it is computationally intensive especially for large transform sizes. In this paper, we have reduced the computation cost of DCT by truncating a couple of least significant bits (LSB), most signi... View full abstract»

• ### Network Science Meets Circuit Theory: Resistance Distance, Kirchhoff Index, and Foster's Theorems With Generalizations and Unification

Publication Year: 2018, Page(s):1 - 14
| | PDF (1223 KB)

The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest... View full abstract»

• ### A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application

Publication Year: 2018, Page(s):1 - 11
| | PDF (3168 KB)

A deep neural network (DNN) online learning processor is proposed with high throughput and low power consumption to achieve real-time object tracking in mobile devices. Four key features enable a low-power DNN online learning. First, a proposed processor is designed with a unified core architecture and it achieves 1.33x higher throughput than the previous state-of-the-art DNN learning processor. S... View full abstract»

• ### An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems

Publication Year: 2018, Page(s):1 - 14
| | PDF (4844 KB)

For a coded massive multi-user multiple-input multiple-output (MIMO) system, a soft-output MIMO detector is essential since it can provide a significant coding gain, e.g., 3 dB, compared with a hard-output detector. However, the computational complexity of the soft-output MIMO detector is usually much greater than that of the hard-output detector. This paper presents the first soft-output message-... View full abstract»

• ### Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Publication Year: 2018, Page(s):1 - 13
| | PDF (3083 KB)

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shap... View full abstract»

• ### A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management

Publication Year: 2018, Page(s):1 - 10
| | PDF (2324 KB)

A programmable voltage detector (PVD) for battery management is proposed to achieve the programmability of the detection voltage (VDETECT). Thanks to the programmability, users can set an appropriate VDETECT for battery management considering the operating voltage of the battery. For batteries including Li-ion and NiMH batteries, a PVD is required to achieve wide programmed VDETECT range from 1.0 ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK