Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007)

10-10 Sept. 2007

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  • Workshop on Fault Diagnosis and Tolerance in Cryptography - Cover

    Publication Year: 2007, Page(s): c1
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  • Workshop on Fault Diagnosis and Tolerance in Cryptography - Title page

    Publication Year: 2007, Page(s):i - iii
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  • Workshop on Fault Diagnosis and Tolerance in Cryptography - Copyright notice

    Publication Year: 2007, Page(s): iv
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  • Workshop on Fault Diagnosis and Tolerance in Cryptography - TOC

    Publication Year: 2007, Page(s):v - vi
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  • Preface

    Publication Year: 2007, Page(s):vii - viii
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  • Program Organization

    Publication Year: 2007, Page(s): ix
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  • Program Committee

    Publication Year: 2007, Page(s): x
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  • Securing Flash Technology

    Publication Year: 2007, Page(s):3 - 20
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    Flash memory is a type of non-volatile semiconductor memory that can be electrically erased and programmed. It can be found in almost every high-capacity consumer electronic device in the market. Examples of such mass memory products include USB flash drives, digital cameras, mobile handsets, set-top boxes for Pay-TV applications, and many more. Some of them use NAND flash technology and others us... View full abstract»

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  • How can we overcome both side channel analysis and fault attacks on RSA-CRT?

    Publication Year: 2007, Page(s):21 - 29
    Cited by:  Papers (21)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    RSA cryptosystem is one of the most widely used algorithms nowadays. However when it is implemented in embedded devices such as smart cards, it can be vulnerable to power analysis attacks and fault attacks. To defeat all known side channel attacks and fault attacks, several countermeasures should be used together. However due to the low computation capability of the embedded devices, we have to fi... View full abstract»

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  • Montgomery Multiplication with Redundancy Check

    Publication Year: 2007, Page(s):30 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    This paper presents a method of adding redundant code to the Montgomery multiplication algorithm, to ensure that a fault attack during its calculation can be detected. This involves having checksums on the input variables that are then used to calculate a valid checksum for the output variable, in a similar manner to that proposed by Walter. However, it is shown that the proposed method is more se... View full abstract»

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  • Fault Detection Structures for the Montgomery Multiplication over Binary Extension Fields

    Publication Year: 2007, Page(s):37 - 46
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    Finite field arithmetic is used in applications like cryptography, where it is crucial to detect the errors. Therefore, concurrent error detection is very beneficial to increase the reliability in such applications. Multiplication is one of the most important operations and is widely used in different applications. In this paper, we target concurrent error detection in the Montgomery multiplicatio... View full abstract»

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  • A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard

    Publication Year: 2007, Page(s):47 - 53
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    The Advanced Encryption Standard, which is used extensively for secure communications, has been accepted recently as a symmetric cryptography standard. However, occurrence of the internal faults by intrusion of the attackers may cause confidential information leak to reveal the secret key. For this reason, several schemes for fault detection of the transformations and rounds in the encryption and ... View full abstract»

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  • A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection

    Publication Year: 2007, Page(s):54 - 61
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    Several techniques have been proposed for encryption blocks in order to provide protection against faults. These techniques usually exploit some form of redundancy, e.g. by means of error detection codes. However, protection schemes that offer an acceptable error detection rate are in general expensive, while temporal redundancy heavily affects the throughput. In this paper, we propose a new desig... View full abstract»

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  • DFA Mechanism on the AES Key Schedule

    Publication Year: 2007, Page(s):62 - 74
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    This paper describes a DFA (differential fault analysis) mechanism on the AES key scheduling process and shows how an entire 128-bit AES key can be retrieved. We make a detailed analysis of the DFA mechanism on the AES key schedule and propose general attack rules. As a result of reconsidering the best attack approach on the basis of analysis, we present a more efficient attack than the previous o... View full abstract»

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  • Countermeasures Against Branch Target Buffer Attacks

    Publication Year: 2007, Page(s):75 - 79
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (130 KB) | HTML iconHTML

    Branch Prediction Analysis has been recently proposed as an attack method to extract the key from software implementations of the RSA public key cryptographic algorithm. In this paper, we describe several solutions to protect against such an attack and analyze their impact on the execution time of the cryptographic algorithm. We show that the code transformations required for protection against br... View full abstract»

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  • Cheap Hardware Parallelism Implies Cheap Security

    Publication Year: 2007, Page(s):80 - 91
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB) | HTML iconHTML

    The paper presents a new aspect within that PC oriented side-channel attack arena. Specifically, we present a novel square vs. multiplication oriented side-channel attack which is very unique to certain simultaneous multi threading CPU architectures and it seems that it cannot be carried out on CPU architectures without SMT hardware assistance. The simple reason for this uniqueness of our novel at... View full abstract»

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  • Passive and Active Combined Attacks: Combining Fault Attacks and Side Channel Analysis

    Publication Year: 2007, Page(s):92 - 102
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (633 KB) | HTML iconHTML

    Side-channel attacks have been deeply studied for years to ensure the tamper resistance of embedded implementations. Analysis are most of the time focused either on passive attack (side channel attack) or on active attacks (fault attack). In this article, a combination of both attacks is presented. It is named PACA for Passive and Active Combined Attacks. This new class of attacks allows us to rec... View full abstract»

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  • Tate Pairing with Strong Fault Resiliency

    Publication Year: 2007, Page(s):103 - 111
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    We present a novel non-linear error coding framework which incorporates strong adversarial fault detection capabilities into identity based encryption schemes built using Tate pairing computations. The presented algorithms provide quantifiable resilience in a well defined strong attacker model. Given the emergence of fault attacks as a serious threat to pairing based cryptography, the proposed tec... View full abstract»

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  • Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations

    Publication Year: 2007, Page(s):112 - 119
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB) | HTML iconHTML

    In this paper we present an register transfer level (RTL) concurrent error detection (CED) technique targeting hardware implementations of elliptic curve cryptography (ECC). The proposed mixed hardware- and time-redundancy based CED techniques use the mathematical properties of the underlying Galois field as well as the ECC primitives to detect both soft errors and permanent faults with low area o... View full abstract»

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  • Author index

    Publication Year: 2007, Page(s): 120
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