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Automation Science and Engineering, IEEE Transactions on

Issue 4 • Date Oct. 2007

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  • Table of contents

    Publication Year: 2007 , Page(s): C1
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  • IEEE Transactions on Automation Science and Engineering publication information

    Publication Year: 2007 , Page(s): C2
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  • Editorial e-Manufacturing in the Semiconductor Industry

    Publication Year: 2007 , Page(s): 485 - 487
    Cited by:  Papers (2)
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    The 11 papers in this special issue focus on e-manufacturing in the semiconductor industry. View full abstract»

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  • A Biochip Microarray Fabrication System Using Inkjet Technology

    Publication Year: 2007 , Page(s): 488 - 500
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2203 KB) |  | HTML iconHTML  

    An automated biological fluid dispensing system for microarray fabrication using inkjet technology is presented in this paper. The hardware of the system consists of a high-precision motion system, a robotic material handling system, computer control systems, and extensive vision systems. The system software includes algorithms to handle control, communication, and manufacturing process information. This fluid dispensing system has been successfully used to produce cDNA microarrays and in the investigation of protein microarray manufacturing. View full abstract»

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  • Economic Efficiency Analysis of Wafer Fabrication

    Publication Year: 2007 , Page(s): 501 - 512
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1603 KB) |  | HTML iconHTML  

    Economic efficiency analysis of semiconductor fabrication facilities (fabs) involves tradeoffs among cost, yield, and cycle time. Due to the disparate units involved, direct evaluation and comparison is difficult. This article employs data envelopment analysis (DEA) to determine relative efficiencies among fabs over time on the basis of empirical data, whereby cycle time performance is transformed into monetary value according to an estimated price decline rate. Two alternative DEA models are formulated to evaluate the influence of cycle time and other performance attributes. The results show that cycle time and yield follow increasing returns to scale, just as do cost and resource utilization. Statistical analyses are performed to investigate the DEA results, leading to specific improvement directions and opportunities for relatively inefficient fabs. Note to Practitioners-Speed of manufacturing is an important metric of factory performance, yet it has long been a challenge to integrate its value into overall performance evaluation. However, for many semiconductor products, a predictable rate of decline in selling prices makes it possible to transform time value into monetary value. This study employs a novel method to incorporate a speed metric into economic efficiency evaluation and thereby provide a guideline for improving fab efficiency in manufacturing practice. Furthermore, this study integrates factory productivity and cycle time into a relative efficiency analysis model that jointly evaluates the impact of these two factors in manufacturing performance. In particular, we validate this approach with data from ten leading wafer fabs obtained by the Competitive Semiconductor Manufacturing Program and we discuss managerial implications. View full abstract»

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  • Queueing Theory for Semiconductor Manufacturing Systems: A Survey and Open Problems

    Publication Year: 2007 , Page(s): 513 - 522
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB) |  | HTML iconHTML  

    This paper surveys applications of queueing theory for semiconductor manufacturing systems (SMSs). Due to sophisticated tool specifications and process flows in semiconductor manufacturing, queueing models can be very complicated. Research efforts have been on the improvement of model assumptions and model input, mainly in the first moment (averages) and the second moment (variations). However, practices show that implementation of classical queueing theory in semiconductor industry has been unsatisfactory. In this paper, open problems on queueing modeling of SMS are discussed. A potential solution is also proposed by relaxing the independent assumptions in the classical queueing theory. Cycle time reduction has constantly been a key focus of semiconductor manufacturing. Compared with simulation, queueing theory-based analytical modeling is much faster in estimating manufacturing system performance and providing more insights for performance improvement. Therefore, queueing modeling attracts generous semiconductor research grants. Unfortunately, existing queueing models focus on simple extensions of the classical queueing theory and fail to question its applicability to the complicated SMS. Hence, related researches have not been employed widely in the semiconductor industry. In this paper, we conduct a survey on the important works and also present some open problems. We also propose a novel solution by relaxing a key assumption in the classical queueing theory. We are currently funded by Intel to explore this potential solution, and we hope it can foster an interesting research field for the years to come. View full abstract»

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  • Practical Extensions to Cycle Time Approximations for the G/G/m-Queue With Applications

    Publication Year: 2007 , Page(s): 523 - 532
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB) |  | HTML iconHTML  

    Approximate closed form expressions for the mean cycle time in a G/G/m-queue often serve as practical and intuitive alternatives to more exact but less tractable analyses. However, the G/G/m-queue model may not fully address issues that arise in practical manufacturing systems. Such issues include tools with production parallelism, tools that are idle with work in process, travel to the queue, and the tendency of lots to defect from a failed server and return to the queue even after they have entered production. In this paper, we extend popular approximate mean cycle time formulae to address these practical manufacturing issues. Employing automated data extraction algorithms embedded in software, we test the approximations using parameters gleaned from production tool groups in IBM's 200 mm semiconductor wafer fabricator. View full abstract»

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  • Expected Response Times for Closed-Loop Multivehicle AMHS

    Publication Year: 2007 , Page(s): 533 - 542
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    We present an analytical approach for estimating the expected time for an automated material handling system (AMHS) to respond to move requests at loading stations in a vehicle-based, unidirectional, closed-loop AMHS. The expected response times are important for estimating the expected work-in-process (WIP) levels at the loading stations for design purposes, and for evaluating the performance of the AMHS as delayed response can impact the production cycle times. The expected response time approximation is validated by comparing the analytical model to the simulation results using a SEMATECH 300 mm hypothetical fab data set. Note to Practitioners - This paper describes an analytic method for estimating the average time for the AMHS to respond to lots ready for movement in a 300 mm wafer fab. The analysis is based on a large-scale model, requires standard solvers, and provides a very fast and reasonably accurate alternative to high-fidelity simulation. It is intended to support the early stage of fab design/redesign, allowing engineers to examine many different options before committing to the time and expense of simulation. View full abstract»

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  • Hierarchical Capacity Planning With Reconfigurable Kits in Global Semiconductor Assembly and Test Manufacturing

    Publication Year: 2007 , Page(s): 543 - 552
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (862 KB) |  | HTML iconHTML  

    Kits (such as accessories, fixtures, jigs, etc.) are widely used in production for many industries. They are normally product- and machine-specific, so a large kit inventory must be maintained when the product-mix variation is high. Fortunately, many kits are reconfigurable. That means they can be dissembled into components and then these components themselves (or together with some other components) can be reassembled into new types of kits. Therefore, we can save money and improve supply chain responsiveness by purchasing components instead of entire kits. However, research on capacity planning with reconfigurable kits has not been reported. We proposed a two-level hierarchical planning methodology to generate a complete capacity planning solution using mixed-integer linear programming. MaxIt covers mid-range monthly planning and automated capacity allocation system covers short-range weekly planning. These systems are integrated to generate optimal capacity plans considering kit components. This methodology has been successfully implemented in Intel's global semiconductor assembly and test manufacturing since 2004. In this paper, we present the hierarchical modeling framework and focus on MaxIt modeling with kit reconfiguration. We also verify the methodology by numerical experiments in a real production environment. View full abstract»

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  • Efficient Simulation-Based Composition of Scheduling Policies by Integrating Ordinal Optimization With Design of Experiment

    Publication Year: 2007 , Page(s): 553 - 568
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1632 KB) |  | HTML iconHTML  

    Semiconductor wafer fab operations are characterized by complex and reentrant production processes over many heterogeneous machine groups with stringent performance requirements. Efficient composition of good scheduling policies from combinatorial options of wafer release and machine dispatching rules has posed a significant challenge to competitive fab operations. In this paper, we design a fast simulation-based methodology by an innovative integration of ordinal optimization (OO) and design of experiments (DOEs) to efficiently select a good scheduling policy for fab operations. Instead of finding the exact performance among scheduling policies, our approach compares their relative orders of performance to a specified level of confidence. Our new approach consists of three stages: performance estimation model construction using DOE, policy option screening process, and final simulation evaluation with intelligent computing budget allocation. The exponential convergence of OO is integrated into all the three stages to significantly improve computational efficiency. Simulation results of applications to scheduling wafer fabrications not only screen out good scheduling policies but also provide insights about how factors such as wafer release and the dispatching of each machine group may affect production cycle times and smoothness under a reentrant process flow. Most of the OO-based DOE simulations require 2-3 orders of magnitude less computation time than those of a traditional approach. Such a high speedup enables decision makers to explore much larger problems. Note to Practitioners - This paper designs a fast simulation-based methodology to compose a good scheduling policy from various dispatching rules of fab operations. The methodology innovatively applies DOE to estimate performance of dispatching rule combinations (policies) over various machines groups in a fab, screens out good enough policy options by using OO over the performance estimation, and al- locates computation time intelligently to simulate potentially good options. Our study shows that OO-based DOE simulations require 2-3 orders of magnitude less computation time than those of a traditional approach. The high speedup enables fab managers to identify good scheduling policies from the many combinations of wafer release and dispatching rules. View full abstract»

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  • Bottleneck Station Scheduling in Semiconductor Assembly and Test Manufacturing Using Ant Colony Optimization

    Publication Year: 2007 , Page(s): 569 - 578
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB) |  | HTML iconHTML  

    In semiconductor assembly and test manufacturing (ATM), a station normally consists of multiple machines (maybe of different types) for a certain operation step. It is critical to optimize the utilization of ATM stations for productivity improvement. In this paper, we first formulate the bottleneck station scheduling problem, and then apply ant colony optimization (ACO) to solve it metaheuristically. The ACO is a biological-inspired optimization mechanism. It incorporates each ant agent's feedback information to collaboratively search for the good solutions. We develop the ACO-based scheduling framework and provide the system parameter tuning strategy. The system implementation at an Intel chipset factory demonstrates a significant machine conversion reduction comparing to a traditional scheduling approach. View full abstract»

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  • A Lot Dispatching Strategy Integrating WIP Management and Wafer Start Control

    Publication Year: 2007 , Page(s): 579 - 583
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    Compound priority dispatching (CPD) is a new dispatching strategy for semiconductor wafer fabrication. It takes into account both work-in-progress (WIP) management and wafer start control. The compound priority of wafers is calculated based upon fab wafer start status, the current processing step, and the amount of WIP in the current, the upstream, and the downstream steps. Simulation results demonstrate that, for a given fab model, CPD can reduce the mean total queue time (MTQT) by 50% and increase the throughput rate by 20% compared with first- in-first-out (FIFO) and shortest remaining processing time (SRPT) scheduling (dispatching) strategies. View full abstract»

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  • A Petri-Net Approach to Modular Supervision With Conflict Resolution for Semiconductor Manufacturing Systems

    Publication Year: 2007 , Page(s): 584 - 588
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1410 KB) |  | HTML iconHTML  

    In a semiconductor manufacturing system, particular human operations may violate desired requirements and lead to destructive failure. For such human-in-the-loop systems, this paper proposes a supervisory framework which guarantees that manual operations meet required specifications so as to prevent human errors in operation using Petri nets. Moreover, a modular technique with an intersection mechanism is proposed in order to cope with the state-space explosion problem of large-scale systems. A rapid thermal process in semiconductor manufacturing systems is provided to show the practicability of the proposed approach. Note to Practitioners - This work was motivated by the requirement of remote monitoring and supervision of semiconductor manufacturing systems. In such human-in-the-loop and large-scale systems, certain human operations may violate desired safety requirements and result in catastrophic failure. Moreover, the overall complexity of most existing Petri net modeling and analysis approaches significantly increases with the size of the considered systems. This paper suggests a modular supervisory scheme for modeling and synthesis of supervisory agents using Petri nets. The proposed method contributes a promising tool for preventing abnormal operations from being carried out to semiconductor manufacturing systems which, if appropriately modified, may be also applied to other types of discrete event systems. View full abstract»

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  • Reticle Design for Minimizing Multiproject Wafer Production Cost

    Publication Year: 2007 , Page(s): 589 - 595
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    Multiproject wafer (MPW) production cost is sensitive to how the chips are arranged in a reticle. In this paper, we propose a methodology for exploring the reticle floorplan design space to minimize MPW production cost. Experimental results show that our methodology often achieves double-digit cost savings. A study using MPW for volume production shows that the volume cutoff points range from a few thousand dice to tens of thousands of dice. Note to Practitioners-This paper proposes a methodology for minimizing MPW production cost via better chip placement in a reticle (called reticle floorplanning). Our methodology consists of an effective reticle floorplanning method, two simulated wafer dicing methods, two cost estimation models, and a procedure for calculating the cost assumed by each project. A design service company or a foundry can use our methodology to reduce MPW production cost and, thus, provides a more affordable and expedient service to its customers. The reticle floorplanning method and simulated wafer dicing methods employed here are the state-of-the-art. A practitioner should adapt these methods to other MPW problems such as dealing with multitechnology process, placing multiple instances of the same design in a reticle, etc. The cost models should also be revised accordingly. The cost data given in this paper should be used only for reference as mask tooling and wafer fabrication costs constantly change. The cost model proposed for calculating the production cost assumed by each project can serve as a basis for developing a fairer pricing model. The study of using MPW for low to medium-volume production is also very useful. It may help a customer deliver its product earlier to market using a low-cost fabrication program. The problem addressed in this paper becomes much simpler if the side-to-side wafer dicing constraint is removed. View full abstract»

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  • T-ASE Reviewers for 2006/2007

    Publication Year: 2007 , Page(s): 596 - 603
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  • Special issue on Visual SLAM

    Publication Year: 2007 , Page(s): 604
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  • Special issue on scientific workflow management and applications

    Publication Year: 2007 , Page(s): 605
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  • 2008 IEEE Conference on Automation Science and Engineering

    Publication Year: 2007 , Page(s): 606
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  • 2007 Index IEEE Transactions on Automation Science and Engineering Vol. 4

    Publication Year: 2007 , Page(s): 607 - 615
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2007 , Page(s): 616
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  • IEEE Robotics and Automation Society Information

    Publication Year: 2007 , Page(s): C3
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  • IEEE Transactions on Automation Science and Engineering Information for authors

    Publication Year: 2007 , Page(s): C4
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T-ASE will publish foundational research on Automation: scientific methods and technologies that improve efficiency, productivity, quality, and reliability, specifically for methods, machines, and systems operating in structured environments over long periods, and the explicit structuring of environments.

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Ken Goldberg
University of California, Berkeley