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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 5 • Date May 1992

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Displaying Results 1 - 10 of 10
  • Conflict free memory addressing for dedicated FFT hardware

    Publication Year: 1992 , Page(s): 312 - 316
    Cited by:  Papers (45)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (412 KB)  

    A multibank memory address assignment for an arbitrary fixed radix fast Fourier transform (FFT) algorithm suitable for high-speed single-chip implementation is developed. The memory assignment is `in place' to minimize memory size and is memory-bank conflict-free to allow simultaneous access to all the data needed for calculation of each of the radix r butterflies as they occur in the alg... View full abstract»

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  • Field 24 amended in b/hAnalysis of mismatch sensitivity in a simulataneously latched CMOS sense amplifier

    Publication Year: 1992 , Page(s): 277 - 292
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1024 KB)  

    A new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in DRAMs, to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bitline load capacitance mismatch is derived. The mathematical methods used in the derivation of the formula are described in detail. The formula yields insight on the DRAM sensing operation. The per... View full abstract»

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  • Fast filter bank (FFB)

    Publication Year: 1992 , Page(s): 316 - 318
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (232 KB)  

    The sliding fast Fourier transform (FFT) filter bank has an exceedingly low complexity of one multiplication per channel per sample. However, its frequency selectivity and passband response are poor. It is shown that the sliding FFT filter bank is in fact a particular member of a new family of fast filter banks (FFBs). In the case of FFT, each cluster of butterflies can in fact be derived from a p... View full abstract»

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  • The analysis of digital integrators for test response compaction

    Publication Year: 1992 , Page(s): 293 - 301
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (732 KB)  

    The compaction properties of integrators that could be used in the built-in self-test (BIST) environment instead of linear finite-state-machine-based comparators are studied. Markov chain models are used to provide a quantitative characterization of the compaction scheme in terms of its steady-state behavior as well as its transient properties. It is demonstrated that the asymptotic fault coverage... View full abstract»

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  • A versatile digitally controlled continuous-time filter structure with wide-range and fine resolution capability

    Publication Year: 1992 , Page(s): 265 - 276
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1144 KB)  

    A digitally programmable and reconfigurable filter structure is presented. The design is based on a versatile continuous-time biquadratic block realized by means of digitally controllable transconductance amplifiers and programmable capacitor arrays. A specific implementation, integrated in a 3 μm p-well CMOS process, which is capable of synthesizing a large number of even-ordered transfer func... View full abstract»

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  • On the implementation of the frequency-domain LMS adaptive filter

    Publication Year: 1992 , Page(s): 318 - 322
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB)  

    Alternative implementations for the frequency-domain LMS adaptive filter are presented. One of the implementations uses an LMS steepest-descent algorithm to compute the discrete Fourier transform (DFT). Therefore, the frequency-domain LMS adaptive filter is implemented as a cascade of two parts, with each one running the LMS adaptive algorithm. This requires fewer computations than the FFT for lar... View full abstract»

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  • VLSI implementation of residue adders based on binary adders

    Publication Year: 1992 , Page(s): 325 - 329
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (356 KB)  

    The implementation of residue number system (RNS) adders based on binary adders is described. These adders use two cycles of addition and support any class of modulus. A technique for choosing the correct sum in a two-cycle residue addition is presented and proved correct. Three VLSI layout approaches for residue adders are described and performance figures for area and speed are given. The two ap... View full abstract»

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  • Complex domain backpropagation

    Publication Year: 1992 , Page(s): 330 - 334
    Cited by:  Papers (62)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (332 KB)  

    The backpropagation algorithm is extended to complex domain backpropagation (CDBP) which can be used to train neural networks for which the inputs, weights, activation functions, and outputs are complex-valued. Previous derivations of CDBP were necessarily admitting activation functions that have singularities, which is highly undesirable. In the derivation, CDBP is derived so that that it accommo... View full abstract»

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  • C-configurability and built-in-test of reconfigurable processor array interconnection networks

    Publication Year: 1992 , Page(s): 302 - 311
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (772 KB)  

    A general-purpose interconnection switch applicable to reconfigurable architectures is described. The switch has been used in the design of reconfigurable architectures and in processor arrays that require reconfigurable interconnections. The reconfigurable switch has the desirable properties that it is both scalable and C-testable. Furthermore, the switch is shown to be C-configurable: that is, t... View full abstract»

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  • An efficient systolic array implementation of the sign-LMS algorithm

    Publication Year: 1992 , Page(s): 322 - 325
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (356 KB)  

    A bit-level systolic array of the implementation of the LMS algorithm is presented. The array is divided into a 2D convolver array and a linear updater array. The structure is 100% data flow efficient, requiring N/2 rows to implement N coefficients. The updater is made up of N/2 simple cells. The sign-LMS algorithm is used for updating the coefficients. All coefficients ... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope