# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 35

Publication Year: 2006, Page(s):c1 - c4
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• ### IEEE Transactions on Circuits and Systems&#8212;I: Regular Papers publication information

Publication Year: 2006, Page(s): c2
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• ### Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

Publication Year: 2006, Page(s):2101 - 2108
Cited by:  Papers (23)  |  Patents (1)
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This paper presents a new detailed analysis of low-voltage differential signaling (LVDS) output buffers that are intended for use in high-speed integrated circuits. Three theoretically possible architectures of a LVDS output driver are discussed in rigorous detail, resulting in the recognition of the most power-conserving circuit configuration. An innovative realization of this identified low-powe... View full abstract»

• ### An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling$SigmaDelta$Modulator and a Flash Converter

Publication Year: 2006, Page(s):2109 - 2124
Cited by:  Papers (18)
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This work proposes an architecture for an analog-to-digital converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits o... View full abstract»

• ### A 1.2- V 30.4-dBm OIP3 Reconfigurable Analog Baseband Channel for UMTS/WLAN Transmitters

Publication Year: 2006, Page(s):2125 - 2131
Cited by:  Papers (12)
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This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN st... View full abstract»

• ### A New Multistage Noise-Shaping Architecture

Publication Year: 2006, Page(s):2132 - 2144
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This paper presents a new architecture for high dynamic range, low oversampling ratio (OSR) noise-shaped digital-to-analog converters (DACs). The instantaneous noise feedforward architecture is a multistage structure in which the instantaneous noise and gain/phase distortion in the first stage are cancelled by passing them through another converter and then subtracting them at the output after ana... View full abstract»

• ### Mixed-Domain Systems and Signal Processing Based on Input Decomposition

Publication Year: 2006, Page(s):2145 - 2156
Cited by:  Papers (21)
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Using input decomposition as a starting point, a variety of new types of systems and signal processors, which mix together domains traditionally kept separate, are derived, and their properties are examined. In one of these systems, digital signals are processed in continuous time, thus avoiding sampling and consequent aliasing, while maintaining the advantages of digital implementations in terms ... View full abstract»

• ### VCO Design With On-Chip Calibration System

Publication Year: 2006, Page(s):2157 - 2166
Cited by:  Papers (21)  |  Patents (1)
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This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arit... View full abstract»

• ### A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

Publication Year: 2006, Page(s):2167 - 2177
Cited by:  Papers (18)
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Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounce... View full abstract»

• ### Adaptive Multiple-Resolution CMOS Active Pixel Sensor

Publication Year: 2006, Page(s):2178 - 2186
Cited by:  Papers (20)  |  Patents (1)
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A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for t... View full abstract»

• ### Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Publication Year: 2006, Page(s):2187 - 2193
Cited by:  Papers (9)  |  Patents (3)
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A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface app... View full abstract»

• ### A 16-Bit Barrel-Shifter Implemented in Data-Driven Dynamic Logic ($D ^3 L$)

Publication Year: 2006, Page(s):2194 - 2202
Cited by:  Papers (18)
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Data-driven dynamic logic (D3L) uses local data instead of a global clock to maintain correct precharge and evaluation phases. Eliminating the clock from dynamic gates yields less power consumption and faster gate operation. Two 16-bit barrel shifters are implemented in a 5-V 0.6-mum CMOS technology: one in normal Domino logic and the other in our proposed D3L. Separate power... View full abstract»

• ### Realization of Boolean Functions via CNN: Mathematical Theory, LSBF and Template Design

Publication Year: 2006, Page(s):2203 - 2213
Cited by:  Papers (17)
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As a paradigm for nonlinear spatial-temporal processing, cellular nonlinear networks (CNN) are biologically inspired systems where computation emerges from a collection of simple locally coupled nonlinear cells. Our investigation is an exploration of an important and difficult aspect of implementing arbitrary Boolean functions by using CNN. A typical class of basic key Boolean functions is the cla... View full abstract»

• ### Admittance Matrix Models for the Nullor Using Limit Variables and Their Application to Circuit Design

Publication Year: 2006, Page(s):2214 - 2223
Cited by:  Papers (45)
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A framework for symbolic analysis and synthesis of linear active circuits has previously been proposed which is based on the use of admittance matrices and infinity-variables. The notation has the important advantage that it can describe both ideal circuit elements, for which an infinite limit is implied, and nonideal circuit elements for which matrix elements are considered finite. The nullor is ... View full abstract»

• ### Fuzzy Impulsive Control of High-Order Interpolative Low-Pass Sigma&#8211;Delta Modulators

Publication Year: 2006, Page(s):2224 - 2233
Cited by:  Papers (8)
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In this paper, a fuzzy impulsive control strategy is proposed. The state vectors that the impulsive controller resets to are determined so that the state vectors of interpolative low-pass sigma-delta modulators (SDMs) are bounded within any arbitrary nonempty region no matter what the input step size, the initial condition and the filter parameters are, the occurrence of limit cycle behaviors and ... View full abstract»

• ### Mitigating ISI Through Self-Calibrating Continuous-Time Equalization

Publication Year: 2006, Page(s):2234 - 2245
Cited by:  Papers (7)  |  Patents (10)
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A method for designing self-calibrating continuous-time equalizers is proposed. Two distinct error terms, generated from the channel pulse response, may be used to adaptively calibrate the equalizer, resulting in a significant reduction of intersymbol interference (ISI). Both error terms are based on the minimization of accumulating ISI versus total ISI. By limiting the change in ISI from bit to b... View full abstract»

• ### Linear Controllers for the Stabilization of Unknown Steady States of Chaotic Systems

Publication Year: 2006, Page(s):2246 - 2254
Cited by:  Papers (18)
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The problem of stabilization of unknown steady states of chaotic systems by means of linear controllers is studied. A complete solution of the problem is given for the case of state feedback stabilization. For the case of output feedback stabilization, some partial results are given. The paper shows that the control theoretic concepts of controllability, stabilizability and root-locus are instrume... View full abstract»

• ### Synthesis of Reduced Equivalent Circuits for Transmission Lines

Publication Year: 2006, Page(s):2255 - 2264
Cited by:  Papers (6)
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This paper presents a method for generating lumped models for symmetrical transmission-line two-ports. These models consist of an ideal transformer and frequency-domain approximations for two physical driving-point impedances. The lumped element values are obtained directly from the distributed parameters or propagation constant and characteristic impedance. The method is applied to dispersive tra... View full abstract»

• ### Robust Stability and Robust Periodicity of Delayed Recurrent Neural Networks With Noise Disturbance

Publication Year: 2006, Page(s):2265 - 2273
Cited by:  Papers (45)
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Neural networks suffer from the natural intra- and inter-cellular noise perturbations and environmental fluctuations. Such noises will undoubtedly affect the dynamics of the neural networks both quantitatively and qualitatively. In this paper, we study the effects of noise perturbations on the stability and periodicity of delayed recurrent neural networks. We first derive the mean-square stability... View full abstract»

• ### Analysis and Design for a Novel Single-Stage High Power Factor Correction Diagonal Half-Bridge Forward AC&#8211;DC Converter

Publication Year: 2006, Page(s):2274 - 2286
Cited by:  Papers (31)
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By means of components placement, the buck-boost and diagonal half-bridge forward converters are combined to create a novel single-stage high power factor correction (HPFC) diagonal half-bridge forward converter. When both the PFC cell and dc-dc cell operate in DCM, the proposed converter can achieve HPFC and lower voltage stress of the bulk capacitor. The circuit analysis of the proposed converte... View full abstract»

• ### Simultaneous Blind Separation of Instantaneous Mixtures With Arbitrary Rank

Publication Year: 2006, Page(s):2287 - 2298
Cited by:  Papers (11)
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This paper presents a gradient-based method for simultaneous blind separation of arbitrarily linearly mixed source signals. We consider the regular case (i.e., the mixing matrix has full column rank) as well as the ill-conditioned case (i.e., the mixing matrix does not have full column rank). We provide one necessary and sufficient condition for the identifiability of simultaneous blind separation... View full abstract»

• ### Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection

Publication Year: 2006, Page(s):2299 - 2305
Cited by:  Papers (6)
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This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fa... View full abstract»

• ### On Synchronization Errors in Networked Feedback Systems

Publication Year: 2006, Page(s):2306 - 2317
Cited by:  Papers (13)
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This paper addresses the problem of synchronization errors and their effects on feedback loops that are closed over communication networks. It is assumed that the feedback loop consists of two discrete-time systems, the clock frequency ratio of which has a special rational form, and is close to one. A Toeplitz matrix approach is taken to model the input/output relationship of the arising feedback ... View full abstract»

• ### Recurrence Plot-Based Approach to the Analysis of IP-Network Traffic in Terms of Assessing Nonstationary Transitions Over Time

Publication Year: 2006, Page(s):2318 - 2326
Cited by:  Papers (10)
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This paper presents a recurrence plot scheme approach to the analysis of nonstationary transition patterns of IP-network traffic. In performing a quantitative assessment of dynamical transition patterns of IP-network traffic, we used the values of determinism (DET) defined by the recurrence quantification analysis (RQA). Also, in evaluating fractal-related properties of IP-network traffic, we empl... View full abstract»

• ### Vector Autoregressive Model-Order Selection From Finite Samples Using Kullback's Symmetric Divergence

Publication Year: 2006, Page(s):2327 - 2335
Cited by:  Papers (20)
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In this paper, a new small-sample model selection criterion for vector autoregressive (VAR) models is developed. The proposed criterion is named Kullback information criterion (KICvc), where the notation vc stands for vector correction, and it can be considered as an extension of the KIC, for VAR models. KICvc adjusts KIC to be an unbiased estimator for the variant of the Kullback symme... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK