# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2006, Page(s):c1 - c4
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• ### IEEE Transactions on Circuits and Systems&#8212;I: Regular Papers publication information

Publication Year: 2006, Page(s): c2
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• ### An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma&#8211;Delta Modulators

Publication Year: 2006, Page(s):1861 - 1868
Cited by:  Papers (12)
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Continuous-time sigma-delta modulators (CTSDMs) may suffer severe performance degradation from the timing error in a quantizer clock. We present an analytical approach to quantify the performance loss due to clock jitter in a CTSDM. Unlike many prior works that model the timing error of clocks as additive white Gaussian phase noise, we propose a jitter model that exhibits an auto-regression form, ... View full abstract»

• ### Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise

Publication Year: 2006, Page(s):1869 - 1884
Cited by:  Papers (81)
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Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of th... View full abstract»

• ### Digital Background Correction of Harmonic Distortion in Pipelined ADCs

Publication Year: 2006, Page(s):1885 - 1895
Cited by:  Papers (65)  |  Patents (2)
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Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration tech... View full abstract»

• ### Improved First-Order Time-Delay Tanlock Loop Architectures

Publication Year: 2006, Page(s):1896 - 1908
Cited by:  Papers (19)
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This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of ... View full abstract»

• ### Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes

Publication Year: 2006, Page(s):1909 - 1917
Cited by:  Papers (12)  |  Patents (13)
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Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we pr... View full abstract»

• ### An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

Publication Year: 2006, Page(s):1918 - 1927
Cited by:  Papers (14)  |  Patents (4)
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A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach whic... View full abstract»

• ### Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques

Publication Year: 2006, Page(s):1928 - 1933
Cited by:  Papers (9)
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This paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering the threshold voltage of its devices. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst case coupling capacitance. Two implementations of this bus architecture are proposed, the... View full abstract»

• ### Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

Publication Year: 2006, Page(s):1934 - 1945
Cited by:  Papers (44)
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Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the ... View full abstract»

• ### Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$

Publication Year: 2006, Page(s):1946 - 1957
Cited by:  Papers (52)  |  Patents (1)
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A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this op... View full abstract»

• ### Small-Signal Modeling and Dynamic Analysis of a Novel ZVZCS Three-Level Converter

Publication Year: 2006, Page(s):1958 - 1965
Cited by:  Papers (8)
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The cyclically switching operation of a novel zero-voltage-zero-current-switching three-level converter is briefly presented. Based on a steady-state time-domain analysis of each equivalent switching topology, an average model is obtained. Small-signal open-loop ac line-to-output, control-to-output, and output-current-to-output-voltage transfer functions are deducted. The stability, gain margin, a... View full abstract»

• ### A Split Vector-Radix Algorithm for the 3-D Discrete Hartley Transform

Publication Year: 2006, Page(s):1966 - 1976
Cited by:  Papers (10)
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In this paper, we propose a three-dimensional (3-D) split vector-radix fast Hartley transform (FHT) algorithm. The main idea behind the proposed algorithm is that the radix-2/4 approach is introduced in the decomposition of the 3-D discrete Hartley transform by using an appropriate index mapping and the Kronecker product. This provides an algorithm based on a mixture of radix-(2times2times2) and r... View full abstract»

• ### Observers-Based Synchronization and Input Recovery for a Class of Nonlinear Chaotic Models

Publication Year: 2006, Page(s):1977 - 1988
Cited by:  Papers (41)
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In this paper, we propose a simple and efficient crypto-system based on a chaotic time delay model. It consists of two steps: the first one assures the transmitter/receiver synchronization while the second step focuses on the encryption/decryption procedure. The synchronization is performed through a non linear state observer design, driven by the transmitted signal. Both full order and reduced or... View full abstract»

• ### A Spectral Model for RF Oscillators With Power-Law Phase Noise

Publication Year: 2006, Page(s):1989 - 1999
Cited by:  Papers (38)
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In this paper, we apply correlation theory methods to obtain a model for the near-carrier oscillator power-spectral density (PSD). Based on the measurement-driven representation of phase noise as a sum of power-law processes, we evaluate closed form expressions for the relevant oscillator autocorrelation functions. These expressions form the basis of an enhanced oscillator spectral model that has ... View full abstract»

• ### On Differential Flatness, Trajectory Planning, Observers, and Stabilization for DC&#8211;DC Converters

Publication Year: 2006, Page(s):2000 - 2010
Cited by:  Papers (30)
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Differential flatness of buck, buck-boost, and boost converter models is shown. Its benefits if used for controlling the output voltage of these converters are revealed by comparing the flatness-based control with passivity-based and linear control. Two observers for the boost converter are suggested one of which requires only the measurement of the converters output voltage. Both observers can be... View full abstract»

• ### Symbolic Framework for Linear Active Circuits Based on Port Equivalence Using Limit Variables

Publication Year: 2006, Page(s):2011 - 2024
Cited by:  Papers (68)
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This paper proposes a new framework for linear active circuits that can encompass both circuit analysis and synthesis. The framework is based on a definition of port equivalence for admittance matrices. This is extended to cover circuits with ideal active elements through the introduction of a special type of limit-variable called the infinity-variable (infin-variable). A theorem is developed for ... View full abstract»

• ### Resonant DC&#8211;DC Converter With Class-E Oscillator

Publication Year: 2006, Page(s):2025 - 2035
Cited by:  Papers (5)
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This paper presents a new free-running-oscillation resonant DC-DC converter with the Class-E oscillator and the Class-E rectifier, along with its design procedure and design curves for any conditions. The proposed converter is a free-running-oscillation system and has no gate-drive circuit to drive the MOSFET. Therefore, the structure of the proposed converter is simpler than that of class E2... View full abstract»

• ### Symmetry Study for Delta- Operator-Based 2-D Digital Filters

Publication Year: 2006, Page(s):2036 - 2047
Cited by:  Papers (13)
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The complexity in the design and implementation of two-dimensional (2-D) filters can be considerably reduced if we utilize the symmetries that might be present in the frequency response of these filters. As the delta-operator formulation of digital filters offers better numerical accuracy and lower coefficient sensitivity in narrowband filter designs when compared to the traditional shift-operator... View full abstract»

• ### Controlled One- and Multidimensional Modulations Using Chaotic Maps

Publication Year: 2006, Page(s):2048 - 2059
Cited by:  Papers (15)
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Recently, several approaches for communications using chaos have been presented, often showing less than acceptable performance. In this paper, a short introduction to the topic is given, and it is shown that such methods can be efficient-if the information production related to the chaos in the transmitter is controlled and used for the payload of the communication. The influence of minimum dista... View full abstract»

• ### EMI Tuning of Hybrid Systems by Periodic Patterns

Publication Year: 2006, Page(s):2060 - 2067
Cited by:  Papers (3)
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Hybrid systems are known to be potential sources of electromagnetic interference due to their principle of recurrently switching voltages and currents. In this paper, we demonstrate different periodic modulation techniques and propose corresponding electromagnetic compatibility optimization methods. A systematic way to optimize finite length modulation sequences is proposed. We prepare mathematica... View full abstract»

• ### Power Analysis of One-Ports Under Periodic Multi-Sinusoidal Linear Operation

Publication Year: 2006, Page(s):2068 - 2074
Cited by:  Papers (5)
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In this paper, a complete theory of the power behavior of one-ports under periodic multi-sinusoidal linear operation is presented. It is based on a time-domain vector space approach in two steps. First, the one-port instantaneous current is decomposed into four orthogonal currents. Second, their power counterparts (absolute powers) are defined as products of norms. Hence, vector and scalar express... View full abstract»

• ### Performance Analysis and Optimization of Multi-User Differential Chaos-Shift Keying Communication Systems

Publication Year: 2006, Page(s):2075 - 2091
Cited by:  Papers (18)
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Bit-error rate (BER) performance of a generalized multi-user differential chaos-shift-keying (DCSK) digital communication system is analyzed and optimized in this paper using baseband models. The generalized version of DSCK involves use of multiple nonrepeating chaotic spreading segments and energy adjustments and allows considerable system optimization. Theoretical BER analysis of correlation dec... View full abstract»

• ### 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

Publication Year: 2006, Page(s): 2092
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• ### IEEE Biomedical Circuits and Systems Conference healthcare technology (BioCAS 2006)

Publication Year: 2006, Page(s): 2093
| PDF (491 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK