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Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug. 2006

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  • Table of contents

    Publication Year: 2006 , Page(s): c1 - 381
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  • IEEE Transactions on Advanced Packaging publication information

    Publication Year: 2006 , Page(s): c2
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  • Novel microcontacts in microwave chip carriers developed by UV-liga process part II

    Publication Year: 2006 , Page(s): 382 - 389
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5104 KB) |  | HTML iconHTML  

    This paper presents the design and development of novel type microcontacts in monolithic microwave integrated circuit (MMIC) chip-carriers to printed circuit board (PCB) assembly. Several new concepts of microcontacts for packaging solutions of microwave and millimeter-wave MMIC are depicted. Simulation and vector network analyzer (VNA) measurement results for these microcontact transitions are discussed. The results show that the electrical parameters are highly dependent on the transition dimensions and substrate features. These contacts are based on male stud (bump) and female (ring) concept. When mating each other, there are clips effect and self-alignment features. Special attention is paid to the shape of the microcontacts in order to facilitate assembly and strengthen the connection. Equivalent electrical circuit is proposed for PSPICE simulation of the dc contact resistance. Finally, the article discusses the technological implementation of the proposed new microcontact stud-ring through low-cost ultraviolet electroplating, lithography, and molding (UV-LIGA) process and the regime influence on the shape, geometry, and mating capabilities. Results from mechanical pull and adhesion tests are also discussed View full abstract»

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  • Chip-package codesign of integrated voltage-controlled oscillator in LCP substrate

    Publication Year: 2006 , Page(s): 390 - 402
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1497 KB) |  | HTML iconHTML  

    This paper presents the design and characterization of a negative resistance type 1.9-GHz oscillator using high quality factor (Q) embedded lumped-element LC passives in an organic-based substrate with liquid crystalline polymer (LCP) dielectric material. A design strategy using analytical models is implemented to determine the value of the base inductance subject to the constraints set by power dissipation. Additionally, the effect of component Qs on the phase noise is qualitatively discussed. This paper also addresses the effects of the parasitics of the surface-mount active devices on the noise spectrum of a negative resistance type voltage-controlled oscillator (VCO). The designed VCO is fully embedded in the LCP substrate and uses high Q on-package passive components. The VCO was measured to operate at 1.92 GHz dissipating 14 mW of dc power and measured a phase noise of -118dBc/Hz and -133 dBc/Hz at 600 KHz and 3-MHz offset, respectively. The high Q of the LC tank circuit was utilized to optimize the VCO to operate from a 2-V supply at bias current of 0.9 mA. Finally, the design and implementation issues in a 2.25-GHz Colpitt's oscillator on LCP substrate are shown. The effects of scaling capacitance ratio on VCO phase noise and on power consumption are verified for the Colpitt's oscillator View full abstract»

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  • Nitride-based flip-chip LEDs with transparent Ohmic contacts and reflective mirrors

    Publication Year: 2006 , Page(s): 403 - 408
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    Nitride-based flip-chip light-emitting diodes (LEDs) with various transparent ohmic contacts and reflective mirrors were fabricated. At 470 nm, it was found that Ni could provide 92% transmittance while Ag could provide 92.4% reflectively. It was also found that the 20-mA forward voltages measured from LEDs with Ni+Ag, Ni+Al, and Ni+Pt were 3.15, 3.29, and 3.18 V while the output powers were 16, 13.3, and 11.6 mW, respectively. Furthermore, it was found that lifetimes of the fabricated flip-chip LEDs were good View full abstract»

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  • Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

    Publication Year: 2006 , Page(s): 409 - 414
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5327 KB) |  | HTML iconHTML  

    This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7degC. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps View full abstract»

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  • Modeling of striplines between a power and a ground plane

    Publication Year: 2006 , Page(s): 415 - 426
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3690 KB) |  | HTML iconHTML  

    In this paper, a stripline model is presented for coupled signal lines routed between a power and a ground plane based on multiconductor transmission line (MTL) theory. Through a suitable diagonalization of the MTL equations for striplines, the transverse electromagnetic (TEM) parallel-plate mode is decoupled from the stripline mode. In this way, stripline models that are obtained assuming ideal planes at ground potential can be extended to take into account the nonideal behavior of the planes. The presented model is applied to represent mode conversion due to vias, holes in the reference planes, and terminations of the stripline. Influence of inhomogeneous media is discussed View full abstract»

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  • A diplexer based on transmission lines, implemented in LTCC

    Publication Year: 2006 , Page(s): 427 - 432
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1470 KB) |  | HTML iconHTML  

    This paper presents a diplexer circuit based on transmission lines. In comparison with other diplexer circuits, the implementation of the proposed diplexer can be easily done on single- as well as multilayer substrates. An implementation example of the presented circuit will be discussed for a global system for mobile communications/digital cellular system (GSM/DCS) application. The diplexer is implemented in a multilayer substrate, using low-temperature cofired ceramics (LTCC) technology. Finally, the simulation results will be compared with the measurements, and it will be shown that they agree excellently. These results and the results out of a sensitivity and yield analysis confirm the excellent behavior of the proposed circuit View full abstract»

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  • On the operation of a press pack IGBT module under short circuit conditions

    Publication Year: 2006 , Page(s): 433 - 440
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5367 KB) |  | HTML iconHTML  

    Press pack insulated gate bipolar transistor (IGBT) modules connected in series for high-voltage direct current (HVDC) converter applications are designed such that when a failure occurs, it occurs in a safe manner by the formation of a stable short circuit, while redundant modules take up the voltage blocking function of the failed module. One such design using individual pressure contacts is described and the events occurring from the initiation of the short circuit to its final failure due to open circuit are reported from an electronics packaging materials design point of view. Experiments to hasten the failure under accelerated test conditions on modules were performed and interrupted at various stages of operation under a short circuit condition. The formation and subsequent aging of the metallurgical alloy under short circuit conditions was investigated by analyzing cross sections of the alloy forming the short circuit. Liquid metal corrosion along with the formation of intermetallics with poor conductivities lead to the final failure by open circuit View full abstract»

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  • Circuit models for power bus structures on printed circuit boards using a hybrid FEM-SPICE method

    Publication Year: 2006 , Page(s): 441 - 447
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB)  

    Power bus structures consisting of two parallel conducting planes are widely used on high-speed printed circuit boards. In this paper, a full-wave finite-element method (FEM) method is used to analyze power bus structures, and the resulting matrix equations are converted to equivalent circuits that can be analyzed using SPICE programs. Using this method of combining FEM and SPICE, power bus structures of arbitrary shape can be modeled efficiently both in the time-domain and frequency-domain, along with the circuit components connected to the bus. Dielectric loss and losses due to the finite resistance of the power planes can also be modeled. Practical examples are presented to validate this method View full abstract»

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  • Room-temperature microfluidics packaging using sequential plasma activation process

    Publication Year: 2006 , Page(s): 448 - 456
    Cited by:  Papers (8)
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    A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical plasma was applied for microfluidics packaging at room temperature. Si/glass and glass/glass wafers were activated by the oxygen RIE plasma followed by nitrogen microwave radicals. Then, the activated wafers were brought into contact in atmospheric pressure air with hand-applied pressure where they remained for 24 h. The wafers were bonded throughout the entire area and the bonding strength of the interface was as strong as the parents bulk wafers without any post-annealing process or wet chemical cleaning steps. Bonding strength considerably increased with the nitrogen radical treatment after oxygen RIE activation prior to bonding. Chemical reliability tests showed that the bonded interfaces of Si/Si could significantly withstand exposure to various microfluidics chemicals. Si/glass and glass/glass cavities formed by the sequential plasma activation process indicated hermetic sealing behavior. SiOx Ny was observed in the sequentially plasma-treated glass wafer, and it is attributed to binding of nitrogen with Si and oxygen and the implantation of N2 radical in the wafer. High bonding strength observed is attributed to a diffusion of absorbing water onto the wafer surfaces and a reaction between silicon oxynitride layers on the mating wafers. T-shape microfluidic channels were fabricated on glass wafers by bulk micromachining and the sequential plasma-activated bonding process at room temperature View full abstract»

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  • Parallel optical transmitter module using angled fibers and a V-grooved silicon optical bench for VCSEL array

    Publication Year: 2006 , Page(s): 457 - 462
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2631 KB) |  | HTML iconHTML  

    We propose an advanced structure of optical subassembly (OSA) for packaging of the vertical-cavity surface-emitting laser (VCSEL) array, using (111) facet mirror of the V-groove ends formed in a silicon optical bench (SiOB) and angled fiber apertures. The feature of our OSA can provide a low optical crosstalk between neighboring channels, a low feedback reflection, and a large misalignment tolerance along the V-groove. We describe the optimized design of fiber angle, VCSEL position, and fiber position. The fabricated OSA structure consists of 12 channels of angled fiber array, 54.7deg V-grooves, Au-coated mirrors on (111) end facet of the V-grooves, and flip-chip-bonded VCSEL array on a SiOB. In this structure, the beam emitted from the VCSEL is deflected at the 54.7deg mirror of (111) end facet and propagated into the angled fiber. The angled fiber array was polished by 57deg. Fabricated OSAs showed a coupling efficiency of 30%-50% that is 25 times larger than that obtained from an OSA with a vertically flat fiber array. Our OSA showed large misalignment tolerance of about 90 mum along the longitudinal direction in the V-groove. We fabricated a parallel optical transmitter module using the OSA and demonstrated 12 channels times2.5 Gb/s data transmission with a clear eye diagram View full abstract»

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  • Fiber pigtailed multimode laser module based on passive device alignment on an LTCC substrate

    Publication Year: 2006 , Page(s): 463 - 472
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2484 KB) |  | HTML iconHTML  

    A concept that utilizes structured planar substrates based on low-temperature cofired ceramics (LTCC) as a precision platform for a miniature passive alignment multimode laser module is demonstrated. The three-dimensional shape of the laminated and fired ceramic substrate provides the necessary alignment structures including holes, grooves, and cavities for the laser-to-fiber coupling. The achieved passive alignment accuracy allows high coupling efficiency realizations of multimode fiber pigtailed laser modules. Thick-film printing and via punching can be incorporated in order to integrate electronic assemblies directly on the optomechanical platform. The platform is scalable, and it allows embedding of subsystems, such as silicon optical bench (SiOB), but it also provides the interface for larger optical systems. Temperature management of high-power laser diodes is achieved by realizing heat dissipation structures and a cooling channel into the LTCC substrate. The measured maximum laser metallization temperature was 70degC when a thermal power of 0.5 W was applied at the laser active area using a liquid cooling of 50 mL/min. The measured maximum temperature of the laser surface was about three times higher without liquid cooling. Optical coupling efficiency of the multimode laser systems was simulated using optical systems simulation software. The nominal coupling efficiency between 100times1 mum stripe laser and 62.5/125-mum graded index fiber (NA=0.275) was 0.37. The simulated coupling efficiency and alignment tolerances were verified by prototype realization and characterization. The measured alignment tolerance values between laser and fiber in AT prototype series were Deltax=7.7 mum, Deltay=7.6 mum, and Deltaz=10.8 mum (SD values). The corresponding values in A2 prototype series were Deltax=3.1 mum, Deltay=9.1 mum, and Deltaz=10.2 mum. The measured average coupling efficiency was 0.28 in AT series and 0.31 in A2 series. The coupling efficiencies of all operati- - onal prototypes varied from 0.05 to 0.43 View full abstract»

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  • Fluxless Flip-Chip Solder Joint Fabrication Using Electroplated Sn-Rich Sn–Au Structures

    Publication Year: 2006 , Page(s): 473 - 482
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5081 KB) |  | HTML iconHTML  

    A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn-Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn-Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn-Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au5Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217degC-222degC. The plated Sn-Au solder bumps on silicon with 50 mum in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited View full abstract»

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  • Nitride-based flip-chip p-i-n photodiodes

    Publication Year: 2006 , Page(s): 483 - 487
    Cited by:  Papers (1)
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    Nitride-based flip-chip p-i-n photodiodes were fabricated and characterized. It was found that we could achieve a small dark current of 5times10-10 A at -5 V and a large rejection ratio larger than three orders of magnitude. It was also found that the photodiodes only detect optical signals with wavelengths between 365 and 378 nm. Furthermore, it was found that peak responsivity occurs at around 370 nm with a value of 0.21 A/W at zero bias which corresponds to 70% external quantum efficiency View full abstract»

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  • Modeling O/E characteristics of 40-gb/s InGaAs side-illuminated waveguide photodiode submodule for optical receivers

    Publication Year: 2006 , Page(s): 488 - 495
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    In this paper, the circuit models of a waveguide photodiode (WGPD) and its submodule were investigated, and the O/E characteristics of a WGPD submodule are examined. Test structures of the WGPD and WGPD submodule were fabricated and microwave return loss (S11) was measured and compared with simulated data to validate the circuit models. With the established submodule model, optical to electrical (O/E) characteristics were measured and compared with the modeled data to analyze the effects of model parameters on the submodule performance. Based on the results, it can be concluded that the suggested submodule model can explain the characteristics of the submodule performance. In addition, parasitic components that originated from the ribbon bonding block can crucially impact on the performance of WGPD submodule View full abstract»

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  • Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

    Publication Year: 2006 , Page(s): 496 - 503
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2160 KB)  

    This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB/lambdag) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed View full abstract»

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  • Embedded power: a 3-D MCM integration technology for IPEM packaging application

    Publication Year: 2006 , Page(s): 504 - 512
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4226 KB)  

    Embedded power (EP) is the name for an integration technology for the power electronics switching stage, in which the multiple bare power chips, such as IGBTs, MOSFETs, and diodes, are buried in a ceramic frame and covered by a dielectric layer with via holes on the Al pads of the chips. Then, a planar metallization pattern is deposited onto it both for bonding to the power chips and a circuit wiring. The ceramic frame can be used as an extra thermal path and substrate for fabrication of the hybrid circuit with compatible thin- or thick-film techniques. When this integrated chips component is stacked with a base substrate and the associated components, a novel three-dimensional (3-D) multichip module (MCM) is produced. Such an integrated power electronics module (IPEM) offers performance improvement, functional integration, and process integration, as compared to conventional power hybrid modules. This paper presents the details of this technology, including the process design and implementation. A subsystem IPEM, incorporating power factor correction (PFC) and dc/dc switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized to demonstrate the feasibility of this power electronics integration technology. The capability for functional integration and the electrical performance improvement, which includes reduction in parasitics and increase in efficiency, are presented View full abstract»

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  • A wafer-level hermetic encapsulation for MEMS manufacture application

    Publication Year: 2006 , Page(s): 513 - 519
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3632 KB) |  | HTML iconHTML  

    In order to simplify the processing complexity and cut down the manufacturing cost, a new wafer bonding technique using ultraviolet (UV) curable adhesive is introduced here for microelectromechanical systems (MEMS) device packaging and manufacturing applications. UV curable adhesive is cured through UV light exposure without any heating process that is suitable for the packaging of temperature-sensitive materials or devices. A Pyrex 7740 glass is chemically wet etched to form microcavities and utilized as the protection cap substrate. After a UV-curable adhesive is spin-coated onto the glass substrate, the substrate is then aligned and bonded through UV light exposure with a device substrate below. Electrical contact pad opening and die separation are done simultaneously by dicing. Two different testing devices, a dew point sensor and capacitive accelerometer, are built to evaluate the package strength and hermeticity. After the dicing process, no structural damage or stiction phenomenon is found in the packaged parallel capacitor. The acceleration test results also indicate that the package using the Loctite 3491 UV adhesive with 150 mum bond width can survive more than 300 days at a 25degC and 100% relative humidity working environment View full abstract»

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  • Adhesive joint design for minimizing fiber alignment shift during UV curing

    Publication Year: 2006 , Page(s): 520 - 524
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    In fiber-optic device packaging using UV curable adhesive bonding, the curing process often causes fiber alignment shift-distortion of the already aligned fiber-optic setups, and thus reduce the assembly yield. A new method for the adhesive joint design for minimizing fiber alignment shift during adhesive curing is reported in this paper. It is demonstrated that for any adhesive, the bonding joint can be designed to alleviate the alignment shift, regardless of adhesives used. The approach provides guideline for high yield and low-cost assembly of fiber-optic devices using adhesive bonding View full abstract»

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  • Package design and materials selection optimization for overmolded flip chip packaging

    Publication Year: 2006 , Page(s): 525 - 532
    Cited by:  Papers (3)
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    In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages View full abstract»

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  • A metallization scheme for junction-down bonding of high-power semiconductor lasers

    Publication Year: 2006 , Page(s): 533 - 541
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2582 KB) |  | HTML iconHTML  

    High-power semiconductor lasers have found increasing applications in industrial, military, commercial, and consumer products. The thermal management of high-power lasers is critical since the junction temperature rise resulting from large heat fluxes strongly affects the device characteristics, such as wavelength, kink power, threshold current and efficiency, and reliability. The epitaxial-side metallization structure has significant impact on the thermal performance of a junction-down bonded high-power semiconductor laser. In this paper, the influence of the epitaxial-side metal (p-metal) on the thermal behavior of a junction-down mounted GaAs-based high-power single-mode laser is studied using finite-element analysis. It is shown that a metallization structure with thick Au layer can significantly reduce the thermal resistance by distributing the heat flow to wider area laterally, and the thermal resistance of a junction-down bonded laser with thick Au metallization is much less sensitive to the voiding in the die attachment solder interface than a laser with thin Au metallization. A metallization structure of Ti-Pt-thick Au-Ti-Cr-Au is designed and implemented, and the metallurgical stability of this metallization scheme is reported. It was found that, without a diffusion barrier, the thick Au layer in the epi-side metallization would be mostly consumed and form intermetallics with the Sn from the AuSn solder during soldering and thermal aging. The Ti-Pt-thick Au-Ti-Cr-Au metallization scheme prevents the diffusion of Sn into the thick Au layer and preserves the integrity of the metallization system. It is a promising candidate for junction-down bonding of high-power semiconductor lasers for improved thermal management and reliability View full abstract»

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  • Electrical characterization of flip-chip interconnects formed using a novel conductive-adhesive-based process

    Publication Year: 2006 , Page(s): 542 - 547
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1111 KB) |  | HTML iconHTML  

    Using conventional microfabrication techniques, we have developed a new, low-cost wafer bumping process that enables a high degree of control over patterning of conductive adhesive interconnects. This approach obviates the need for development of dispensing and scraping head equipment that may otherwise be required for mass fabrication of lithographically patterned adhesive bumps. Flip-chip interconnects formed using this new process offer better electrical performance as compared to those formed by squeegee-based definition techniques. This is inferred in this paper by experimentally demonstrating lower contact resistance with the polished bumps as compared to the squeegeed bumps. Furthermore, in order to study the high-speed electrical performance characteristics of these conductive adhesive bumps, a 10-GHz 1.55-mum p-i-n photodetector fabricated in the antimonide material system was used as case study. The results from the bandwidth characterization of the polymer flip-chip-integrated detector showed minimum degradation in the high-speed performance characteristics of the detector View full abstract»

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  • Modeling and measurement of simultaneous switching noise coupling through signal via transition

    Publication Year: 2006 , Page(s): 548 - 559
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1002 KB) |  | HTML iconHTML  

    The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach View full abstract»

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  • Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines

    Publication Year: 2006 , Page(s): 560 - 569
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4632 KB) |  | HTML iconHTML  

    Differential signaling has become a popular choice for multigigabit digital applications in favor of its low-noise generation and high common-mode noise immunity. Recalling from the full-wave solution of S-parameters, this paper presented a design methodology of analysis scheme to extract the equivalent circuits of discontinuities observed on the strongly coupled differential lines. Signal integrity effects of the bent differential transmission lines in a high-speed digital circuit were then simulated in the time domain. A dual back-to-back routing topology of bent differential lines to reduce the common-mode noise was further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance was also proposed. Furthermore, the comparison between the simulation and measured results validated the equivalent circuit model, coupled bends with compensation capacitance patch, and analysis approach View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering