24th IEEE VLSI Test Symposium

April 30 2006-May 4 2006

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  • Proceedings. 24th IEEE VLSI Test Symposium

    Publication Year: 2006, Page(s): c1
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  • 24th IEEE VLSI Test Symposium - Title

    Publication Year: 2006, Page(s):i - iii
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  • 24th IEEE VLSI Test Symposium - Copyright

    Publication Year: 2006, Page(s): iv
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  • 24th IEEE Symposium on Reliable Distributed Systems - Table of contents

    Publication Year: 2006, Page(s):v - xi
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  • Forward

    Publication Year: 2006, Page(s): xii
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  • Organizing Committee

    Publication Year: 2006, Page(s):xii - xv
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  • Program Committee

    Publication Year: 2006, Page(s): xvi
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  • Program Committee

    Publication Year: 2006, Page(s): xvii
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  • Reviewers

    Publication Year: 2006, Page(s): xviii
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  • Acknowledgments

    Publication Year: 2006, Page(s): xix
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  • Test Technology Technical Council (TTTC)

    Publication Year: 2006, Page(s): xx
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  • Test Technology Educational Progam (TTEP) Tutorials

    Publication Year: 2006, Page(s): xxiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (55 KB)

    Summary form only for tutorial. View full abstract»

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  • Awards

    Publication Year: 2006, Page(s):xxvii - xxix
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  • The impacts of untestable defects on transition fault testing

    Publication Year: 2006, Page(s):6 pp. - 7
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    In this paper, we investigate the impacts of the untestable defects, modeled by stuck-open faults and bridging faults, on the quality of transition fault test set. The presence of those defects may make some transition faults to be tested invalidly if they are not considered during transition fault test generation. As a result, the chips with delay defects may escape from testing. Two incremental ... View full abstract»

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  • Low-cost scan-based delay testing of latch-based circuits with time borrowing

    Publication Year: 2006, Page(s):8 pp. - 15
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (465 KB) | HTML iconHTML

    Classical test approaches typically provide abysmally low path delay fault coverage for high-speed latch-based circuits where time borrowing may occur. Furthermore, none of the classical design-for-testability (DFT) approaches can be used to improve coverage. In [Chung, 2003] we proposed the first structural testing approach that can provide high robust path delay fault coverage for such circuits.... View full abstract»

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  • Path delay fault simulation on large industrial designs

    Publication Year: 2006
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to... View full abstract»

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  • A scheme for on-chip timing characterization

    Publication Year: 2006
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    We present a novel technique for performing post-silicon timing characterization, i.e., delay fault test and debug, using on-chip delay measurement of critical paths in Integrated Circuits. In Deep Submicron technologies, timing related failures have become a major source of defective silicon, making it imperative to carry out efficient delay fault testing on such chips. In addition to test, there... View full abstract»

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  • BIST for network-on-chip interconnect infrastructures

    Publication Year: 2006, Page(s):6 pp. - 35
    Cited by:  Papers (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootst... View full abstract»

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  • Mixed PLB and interconnect BIST for FPGAs without fault-free assumptions

    Publication Year: 2006, Page(s):6 pp. - 43
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB) | HTML iconHTML

    We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop strong BIST methods for one class of components (PLBs or interconnects) while assuming that the other class is fault-free. This results in a cyclical conundrum that renders current PLB and interconnect BIST techniques imprac... View full abstract»

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  • Session Abstract

    Publication Year: 2006, Page(s): 44
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    Achieving excellent reliability at reasonable cost is a daunting challenge for high-performance processors on advanced technologies. Major issues are lack of high/low voltage margin, huge leakage currents (particularly at burn-in/stress voltages and temperatures) and new failure modes. In this session, we will have three presentations from industry experts who are on the front lines working on the... View full abstract»

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  • Thermal-aware testing of network-on-chip using multiple-frequency clocking

    Publication Year: 2006, Page(s):6 pp. - 51
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB) | HTML iconHTML

    Chip overheating due to excessive and unbalanced power dissipation has become a critical problem during test of complex core-based systems. In this paper, we address the overheating problem in network-on-chip systems by using on-chip multiple-frequency clocking. We control the core temperatures during test scheduling by varying the test clock frequency assigned to each core, so that the power diss... View full abstract»

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  • PEAKASO: peak-temperature aware scan-vector optimization

    Publication Year: 2006
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors, hotspot is predicted by window-based power analysis. The peak temperature on the hotspot is minimized by global scan vector ordering which expedites heat dissipation to ambient air through large thermal gradient. Further pe... View full abstract»

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  • A new ATPG method for efficient capture power reduction during scan testing

    Publication Year: 2006, Page(s):6 pp. - 65
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but a... View full abstract»

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  • Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive

    Publication Year: 2006, Page(s):6 pp. - 71
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate m... View full abstract»

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  • Iterative OPDD based signal probability calculation

    Publication Year: 2006, Page(s):6 pp. - 77
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    This paper presents an improved method to accurately estimate signal probabilities using ordered partial decision diagrams (OPDDs) [Kodavarti 93] for partial representation of the functions at the circuit lines. OPDDs which are limited to a certain maximum number of nodes are built iteratively with different variable orderings to efficiently explore different regions of the function. Signal probab... View full abstract»

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