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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 8 • Date Aug. 2005

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Displaying Results 1 - 25 of 31
  • Table of contents

    Publication Year: 2005 , Page(s): c1 - c4
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  • IEEE Transactions on Circuits and Systems–I: Regular Papers publication information

    Publication Year: 2005 , Page(s): c2
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  • Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications

    Publication Year: 2005 , Page(s): 1481 - 1488
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8- \mu\hbox {m} , CMOS process. The power consumption of the OTA remains below 1 \mu W for biasing currents in the range between 1–200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors. View full abstract»

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  • Analysis and Design of Low-Distortion CMOS Source Followers

    Publication Year: 2005 , Page(s): 1489 - 1501
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    This paper presents the analysis of CMOS technology based nMOS source follower (NSF), pMOS source follower (PSF), and cascade-complementary source follower(CCSF) using a simplified large-signal model. Three new large-signal second harmonic equations and high-frequency transfer functions are derived. Optimization strategies which permit optimal design for low-distortion NSF, PSF, and CCSF are proposed. This includes a new complementary linearization method introduced for CCSF. With employment of dedicated optimization, the CCSF can achieve significantly better low-distortion broad-band characteristics than the other schemes. Comparative HSPICE simulated results for the three source followers have shown good agreement with the second-order analytical results using the simplified BSIM3 model equations. View full abstract»

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  • Continuous-Time Time-Stretched Analog-to-Digital Converter Array Implemented Using Virtual Time Gating

    Publication Year: 2005 , Page(s): 1502 - 1507
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    We demonstrate the continuous-time operation of a time-stretch analog-to-digital converter array. A continuous-time RF signal is segmented into parallel channels and each channel is stretched in time prior to digitization. The technique offers improvement in the effective input bandwidth and sampling rate of the digitizer. The implementation uses virtual time gating for interleaving segments of the continuous-time RF signal. The signal is first modulated onto a linearly chirped optical carrier and then sliced, in time, using passive optical filters. This technique obviates the need for fast switching gates. It results in minimum interchannel mismatch and in hardware efficiency since all channels are stretched using the same electro-optic modulator and the same dispersive elements. View full abstract»

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  • Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme

    Publication Year: 2005 , Page(s): 1508 - 1514
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. View full abstract»

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  • A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator

    Publication Year: 2005 , Page(s): 1515 - 1525
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB) |  | HTML iconHTML  

    This paper intends to give an insight into the potentials and tradeoffs when designing cascaded, continuous-time (CT) sigma-delta modulators. Therefore, a case study is presented considering the implementation of a 2-1-1 CT modulator. The nonideal behavior is regarded in detail and an automatic gain-error cancellation is presented. Finally, a circuit board implementation is presented, which has been chosen to verify the automatic error correction. It turns out that despite a more critical behavior than in the discrete-time (DT) case, cascaded CT modulators have the potential, to realize high bandwidth, high resolution analog-to-digital (A/D) converters in future integrated designs. View full abstract»

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  • An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool

    Publication Year: 2005 , Page(s): 1526 - 1534
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-the-art evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35- \mu\hbox {m} 5M2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 2.3 V. The power-added efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved. View full abstract»

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  • GBOPCAD: A Synthesis Tool for High-Performance Gain-Boosted Opamp Design

    Publication Year: 2005 , Page(s): 1535 - 1544
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6- \mu m CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60 ^\circ phase margin and a 0.0244% settling time of 5 ns. The sample/hold front-end of a 12-bit 50-MSample/s analog–digital converter was implemented with this opamp. It achieves a signal-to-noise ratio of 81.9 dB for a 8.1-MHz input signal. View full abstract»

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  • Design and Comparison of Very Low-Voltage CMOS Output Stages

    Publication Year: 2005 , Page(s): 1545 - 1556
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    This paper analyzes and compares CMOS output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations. View full abstract»

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  • Efficient Addition Circuits for Modular Design of Processors-in-Memory

    Publication Year: 2005 , Page(s): 1557 - 1567
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB) |  | HTML iconHTML  

    This paper presents the design of a new dynamic modular addition circuit optimized for the integration into high-speed low-power processors-in-memory (PIMs). The proposed architecture is based on a hybrid ripple-carry/carry-look ahead/carry-bypass approach. In order to reach the required computational speed and the limited power dissipation, the circuit described here is divided into two independent submodules interfaced through dynamic latches. Furthermore, the proposed adder operates in the single instruction multiple data fashion, therefore it is able to manage different operand wordlengths. Our PIM architecture is based on slices containing 16-bit adders. Therefore, the main specification of the design described here is to minimize the effect on speed performance caused by cascading 16-bit blocks. Using a bulk CMOS UMC 0.18- \mu\hbox {m} 1.8-V process, the optimized version of the 64-bit circuit here proposed, obtained realizing a rippling chain of four 16-bit blocks, shows a power-delay product of only 38.8 \hbox {pJ$^\ast$ }\hbox {ns} and requires less than 4300 transistors. View full abstract»

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  • Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design

    Publication Year: 2005 , Page(s): 1568 - 1579
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB) |  | HTML iconHTML  

    An efficient implementation of discrete cosine transform (DCT) computations are presented based on the so-called shifted discrete Fourier transform (SDFT), a generalization of the conventional DFT (DFT). Due to the simple form of the factorized matrices, the derived architecture can be easily constructed from the cascade of only two types of parameterized hardware modules: butterfly operators and rotators. The butterfly operator performs the conventional butterfly shuffling and addition/subtraction. The rotator that performs plane rotations of two-dimensional (2-D) vectors is designed using carry-save-adder (CSA)-based unfolded pipelined CORDIC architecture where the rotation angles can be approximated with different accuracies using a sequence of bipolar signs. The proposed one-dimensional and 2-D DCT implementations composed of the above two types of parameterized modules can be used as flexible and reusable Silicon Intellectual Property (SIP) for the DCT computation unit to be embedded in system-on-a-chip (SoC) design. The proposed implementations have many features and advantages, including SIP reusability, low complexity, high-throughput, regularity, scalability (easy extension of transform length), and flexibility (approximated DCT with various accuracies). View full abstract»

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  • Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies

    Publication Year: 2005 , Page(s): 1580 - 1589
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    As scaling of silicon devices continues at an aggressive pace, the problems associated with it are becoming more and more evident. With “short-channel effects” already in the way of scaling, interest has shifted to the possible use of nonsilicon molecular devices for circuit implementation. Carbon nanotube has emerged as a promising candidate. However, molecular devices such as carbon nanotube field-effect transistors (CNFETs) with their super-scaled dimensions and high current densities would increase the power density on chip and reasonable predictions estimate that they would far exceed the maximum power density limitation [1] . This paper explores the use of energy-recovery techniques in molecular CNFET based digital circuits and demonstrates how they can alleviate the power density problem in such circuits. View full abstract»

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  • Quantum Computer Simulator Based on the Circuit Model of Quantum Computation

    Publication Year: 2005 , Page(s): 1590 - 1596
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    A quantum computer simulator is presented. This simulator is an engineering work and no deep understanding of quantum mechanics is required from the user. The simulator is based on the circuit model of quantum computation in which quantum gates act on quantum registers which comprise a number of quantum bits (qubits). The inputs to the simulator are the initial states of the qubits that form a quantum register and the quantum gates applied at each computation step. The inputs are entered through a graphical user interface. The outputs of the simulator are the matrices that represent the quantum register state at each quantum computation step and graphical outputs that show the probability of measuring each one of the possible quantum register base states and the phase of each state at each computation step. The well-known Deutsch's algorithm and the quantum Fourier transform, which is the base of many quantum algorithms, are presented using this simulator. Furthermore, the generation and variation of entanglement during quantum computations can be calculated using this simulator. The quantum computer simulator is a useful tool for the study of quantum computer circuits, quantum computing, and the development of new quantum algorithms. View full abstract»

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  • A Distributed Synchronized Clocking Method

    Publication Year: 2005 , Page(s): 1597 - 1607
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    This paper will present a novel method to generate and distribute a synchronous clock to multiple nodes in a distributed system. Total system synchronization is established by adjusting the internal delays of each node so that the delay between all adjacent pairs of nodes becomes identical. The system is based on the principles of phase-locked and delay-locked loops but does not discuss the methods and details of phase acquisition, jitter or lock-in time. The system is composed of a master node used to generate clock pulses and multiple slave nodes used to align the pulses. A Matlab Monte Carlo simulation of the linear behavior of the system is presented which not only validates the theoretical description, but also can be used as a good tool to gauge the performance of any particular system scenario. Selected HSpice simulations are then presented which show the operating characteristics of certain scenarios involving differing interconnect lengths between nodes that correspond to specific Matlab simulations. View full abstract»

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  • Generalized Low-Error Area-Efficient Fixed-Width Multipliers

    Publication Year: 2005 , Page(s): 1608 - 1619
    Cited by:  Papers (44)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1496 KB) |  | HTML iconHTML  

    In this paper, we extend our previous methodology for designing a family of low-error area-efficient fixed-width two's-complement multipliers that receive two n -bit numbers and produce an n -bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to low-error area-efficient fixed-width multipliers suitable for very large-scale integration implementation and digital signal processing application. Via the proposed Type 1 8 \times 8 fixed-width multiplier, the reduction of the average error can be improved by 88% compared with the direct-truncated (D-Truncated) multiplier. It is also shown that the same proposed multiplier leads to 32.75% reduction in area compared with the standard multiplier. View full abstract»

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  • Perturbation analysis of nonlinear distortion in analog integrated circuits

    Publication Year: 2005 , Page(s): 1620 - 1631
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB) |  | HTML iconHTML  

    A method for predicting the distortion in weakly nonlinear analog circuits is presented, which relies on the classical theory of regular perturbation. Accordingly, a nonlinear circuit is described and analyzed as a perturbation of its linearized model, and the response to a periodic signal is analytically calculated through frequency-domain recurrent formulas. The method is simple and quite straightforward to apply, as it involves the calculation of frequency-domain transfer functions and of Fourier coefficients only, making it easily adaptable to any circuit topology. The method can be a valid alternative to the Volterra series method. A relationship between the proposed method and the Volterra series method is established, showing that they lead to very similar approximants to the solution. The method has been numerically tested in practical circuits wherein the devices are modeled by polynomial and exponential nonlinearities. View full abstract»

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  • Symbolic Analysis of Switching Systems: Application to Bifurcation Analysis of DC/DC Switching Converters

    Publication Year: 2005 , Page(s): 1632 - 1643
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    A symbolic method is proposed in this paper for analyzing the bifurcation behavior of switching nonsmooth systems. The proposed method focuses on the symbolic sequence describing the topological change of the system which characterizes its bifurcation behavior. The concept of block sequence is first introduced. Based on the block sequence, the smoothness of the PoincarÉ map is described. Moreover, two main theorems are given to detect border collision and standard bifurcations. Finally, a specific example of the buck switching converter is presented to illustrate the application of the proposed symbolic analysis method. Using the proposed method, two-dimensional (2-D) bifurcation diagrams, which can assist engineers in identifying regions of preferred or undesired operations in the select parameter space, can be easily obtained. View full abstract»

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  • Fault Detection and Diagnosis for General Stochastic Systems Using B-Spline Expansions and Nonlinear Filters

    Publication Year: 2005 , Page(s): 1644 - 1652
    Cited by:  Papers (56)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    This paper presents a new fault detection and diagnosis (FDD) algorithm for general stochastic systems. Different from the classical FDD design, the distribution of system output is supposed to be measured rather than the output signal itself. The task of such an FDD algorithm design is to use the measured output probability density functions (PDFs) and the input of the system to construct a stable filter-based residual generator such that the fault can be detected and diagnosed. For this purpose, square root B-spline expansions are applied to model the output PDFs and the concerned problem is transformed into a nonlinear FDD algorithm design subjected to a nonlinear weight dynamical system. A linear matrix inequality based solution is presented such that the estimation error system is stable and the fault can be detected through a threshold. Moreover, an adaptive fault diagnosis method is also provided to estimate the size of the fault. Simulations are provided to show the efficiency of the proposed approach. View full abstract»

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  • A Chopper Stabilized Biasing Circuit Suitable for Cascaded Wheatstone-Bridge-Like Sensors

    Publication Year: 2005 , Page(s): 1653 - 1665
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    Many sensitive devices are based on Wheatstone bridge structures or can be modeled as Wheatstone bridges like Hall effect magnetic sensors. These sensors require a biasing circuit, and many solutions were proposed. However, up to now, none of them gives the opportunity to cascade several sensors, while such a cascade can help in improving the signal-to-noise-ratio (SNR) or in removing some parasitic effects through the direct summing/subtraction of sensing/parasitic effects. The circuit this paper presents is based on an operational transconductance amplifier with n output stages, and allows to cascade n Wheatstone-bridge-like sensors. It is shown that the maximal number of bridges which can be efficiently cascaded is limited by the output resistance of the output stages. Nevertheless, this number remains sufficient in practical cases, easily up to n=10 . To remove the 1/f noise coming from the output stages, a chopper stabilization is used. We also establish formulas which allow quick hand calculation of the main parameters of the circuit. A prototype where 10 Hall effect sensors are cascaded is presented as well as experimental results. View full abstract»

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  • Interleaved Buck Converters Based on Winner-Take-All Switching

    Publication Year: 2005 , Page(s): 1666 - 1672
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    This paper studies basic interleaved buck converters using a switching rule based on a winner-take-all principle. As the parameters are selected suitably, the system can realize multiphase synchronization automatically which is convenient for the ripple reduction of the output current. As the parameters vary, the system exhibits a variety of synchronous phenomena. Using the piecewise-constant model, we give the parameter condition theoretically for existence and stability of the synchronous phenomena. The simple test circuit is presented and typical synchronous phenomena are confirmed experimentally. View full abstract»

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  • Low-Order IIR Filter Bank Design

    Publication Year: 2005 , Page(s): 1673 - 1683
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    The advantage of infinite-impulse response (IIR) filters over finite-impulse response (FIR) ones is that the former require a much lower order (much fewer multipliers and adders) to obtain the desired response specifications. However, in contrast with well-developed FIR filter bank design theory, there is no satisfactory methodology for IIR filter bank design. The well-known IIR filters are mostly derived by rather heuristic techniques, which work in only narrow design classes. The existing deterministic techniques usually lead to too high order IIR filters and thus cannot be practically used. In this paper, we propose a new method to solve the low-order IIR filter bank design, which is based on tractable linear-matrix inequality (LMI) optimization. Our focus is the quadrature mirror filter bank design, although other IIR filter related problems can be treated and solved in a similar way. The viability of our theoretical development is confirmed by extensive simulation. View full abstract»

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  • Design of Symmetrical Class E Power Amplifiers for Very Low Harmonic-Content Applications

    Publication Year: 2005 , Page(s): 1684 - 1690
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    Class E power amplifier circuits are very suitable for high efficiency power amplification applications in the radio-frequency and microwave ranges. However, due to the inherent asymmetrical driving arrangement, they suffer significant harmonic contents in the output voltage and current, and usually require substantial design efforts in achieving the desired load matching networks for applications requiring very low harmonic contents. In this paper, the design of a Class E power amplifier with resonant tank being symmetrically driven by two Class E circuits is studied. The symmetrical Class E circuit, under nominal operating conditions, has extremely low harmonic distortions, and the design of the impedance matching network for harmonic filtering becomes less critical. Practical steady-state design equations for Class E operation are derived and graphically presented. Experimental circuits are constructed for distortion evaluation. It has been found that this circuit offers total harmonic distortions which are about an order of magnitude lower than those of the conventional Class E power amplifier. View full abstract»

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  • Statistical Performance of the Memoryless Nonlinear Gradient Algorithm for the Constrained Adaptive IIR Notch Filter

    Publication Year: 2005 , Page(s): 1691 - 1702
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Gradient-type algorithms for the adaptive infinite-impulse response (IIR) notch filters are very attractive in terms of both performance and computational requirements for various real-life applications. This paper presents, in detail, a statistical analysis of the memoryless nonlinear gradient (MNG) algorithm applied to the well-known second-order adaptive IIR notch filter with constrained poles and zeros. This analysis is based on a proper use of Taylor series expansion and nonlinearization of output signals of the notch and gradient filters. Two difference equations are derived first for the convergence in the mean and mean square senses, respectively. Two closed-form expressions, one for the steady-state estimation bias and the other for the mean-square error, are then derived based on the difference equations, with the former valid for both fast and slow adaptations and the latter valid for slow adaptation only. A closed-form coarse stability bound for the step size parameter of the algorithm is also derived. Extensive simulations are performed to reveal the validity and limitations of the analytical findings. Comparisons between the MNG and the conventional plain gradient algorithm are also made. View full abstract»

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  • Special issue on advances on life science systems and applications

    Publication Year: 2005 , Page(s): 1703
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras