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Circuits and Systems, IEEE Transactions on

Issue 10 • Date Oct 1990

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Displaying Results 1 - 21 of 21
  • On computing 2-D systolic algorithm for discrete cosine transform

    Publication Year: 1990 , Page(s): 1321 - 1323
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    A 2-D systolic array algorithm for the discrete cosine transform (DCT) is presented. It is based on the inverse discrete Fourier transform (DFT) version of the Goertzel algorithm via Horner's rule. This array requires N cells and multipliers, takes √N +2 clock cycles to produce a complete N-point DCT, and is able to process a continuous stream of data sequences View full abstract»

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  • Shape determination from intensity images-a new algorithm

    Publication Year: 1990 , Page(s): 1248 - 1257
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    An algorithm for determining surface shapes from intensity measurements is presented. Assuming a point-surface illumination and a Lambertian surface, a model that allows for the estimation of the normals at any point on the surface as well as the depth at any point in the image plane along the viewer (camera) direction is developed. Explicit shape descriptors are derived for local characterization of the surface at any point. Studies with synthetic and natural scenes indicate that surface-shape descriptors are shown to provide a reliable local characterization of the surface at any point on the surface within the occluding boundaries View full abstract»

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  • Note the window function with nearly minimum sidelobe energy

    Publication Year: 1990 , Page(s): 1323 - 1324
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    It is shown that a previously published class of window functions is complementary to the Chebyshev window function. The impulse response coefficients are expressed in closed form. Chebyshev window functions of the first and second kind are discussed View full abstract»

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  • A note on general gain-sensitivity product and complementary transformation

    Publication Year: 1990 , Page(s): 1324 - 1325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    It is shown that the general gain-sensitivity product ΓTA does not change after performing complementary transformation in a linear feedback system with a single op amp View full abstract»

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  • Polynomial evaluation in VLSI using distributed arithmetic

    Publication Year: 1990 , Page(s): 1299 - 1304
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Alternate formulations of Horner's rule which partitions the algorithm into inner-product computations are studied. Fixed-point inner products may be implemented with distributed arithmetic structures that use table-lookup in place of multiplication. Distributed arithmetic can be smaller and faster than lumped arithmetic in technologies where memory is cheaper than logic. The partitioned algorithms may be mapped to mesh-connected or tree-connected VLSI architectures. The partitions may be chosen to optimize cost measures and constraints that are functions of area, latency, period, and arithmetic precision. These structures are compared with a tree structure for polynomial evaluation. It is considered that each has advantages depending on problem size and target technology View full abstract»

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  • Linear array processors for 2-D FIR and IIR digital filters

    Publication Year: 1990 , Page(s): 1291 - 1296
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    Several linear-array processors are developed for two-dimensional (2-D) finite impulse response (FIR) and infinite impulse response (IIR) digital filters. The input signal is processed in a column-by-column scheme, thus an extremely high processing speed is reached. The speed is high enough for real-time image processing and computer vision. The array processors possess high regularity, simple data-communication schemes, simple control, and data-driven format. The number of processing elements (PEs) can be changed according to applications. The array processor for IIR filtering is developed by combining the uses of the new array processors for 2-D FIR filtering and existing array processors for 1-D IIR filtering View full abstract»

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  • An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range

    Publication Year: 1990 , Page(s): 1284 - 1288
    Cited by:  Papers (30)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    It is shown that the depletion-mode linear resistor of Babanezhad and Temes (IEEE J. Solid-State Circuits, vol. SC-19, p.932-8, 1984) can be implemented in enhancement-mode devices. This allows a large increase in the dynamic range of the resistors. By inserting a bias source, the linearity can also be improved. A layout and experimental results on the resulting IC are included View full abstract»

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  • A technique for improving the accuracy and the speed of CMOS current-cell DAC

    Publication Year: 1990 , Page(s): 1325 - 1327
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    A new switching technique for improving the accuracy and speed of CMOS current-cell digital to analog converters (DACs), called the incremental-switching technique, is described. The maximum accuracy and speed of DACs using the incremental-switching technique are higher than 10 b and 1 GHz, respectively View full abstract»

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  • An analysis of coefficient inaccuracy for 2-D FIR direct form digital filters

    Publication Year: 1990 , Page(s): 1308 - 1313
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    Filter frequency errors due to coefficient quantization in direct-form realization of zero-phase two-dimensional finite impulse-response (2-D FIR) digital filters are analyzed. Applying a previously published method for 1-D FIR digital filters, the case of 2-D FIR filters with octagonal or quadrantal symmetry is considered. Based on the analysis, statistical bounds on the frequency-response errors and on the wordlength of the filter coefficients are developed and verified by experimental data View full abstract»

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  • Frequency domain analysis of Hopf bifurcations in electric power networks

    Publication Year: 1990 , Page(s): 1317 - 1321
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    An approach to studying certain types of parametric instabilities in electric power networks that are associated with a Hopf bifurcation is discussed. A particular frequency-domain version of the Hopf bifurcation theorem is used to complete an example of power-system flutter instability. It is shown that the instability encountered therein is a Hopf bifurcation and that it is supercritical. The results of the analysis are verified by computer simulation View full abstract»

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  • Analysis and synthesis of neural networks with lower block triangular interconnecting structure

    Publication Year: 1990 , Page(s): 1267 - 1283
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1140 KB)  

    A qualitative analysis of Hopfield-type neural network models with lower block triangular interconnecting structure is presented. Such networks are viewed as interconnected systems and the results are phrased in terms of the qualitative properties of the subsystems of the networks and in terms of the properties of the interconnecting structure of the networks. The results address the stability properties of equilibrium points and estimates of trajectory properties. A design method is devised for this class of neural networks to establish desired relationships between scalar-valued analog input signals and output signals in binary form. The applicability of the design methodology is demonstrated by means of several specific examples, including the design of an A/D converter, the design of a resistor sorter, and the design of a resister tolerancer. Specific simulations show that the present design method offers significant improvements over other design techniques that employ Hopfield neural networks View full abstract»

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  • IIR partial response digital filter design with equiripple stopband attenuation (class I)

    Publication Year: 1990 , Page(s): 1209 - 1216
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    The design of infinite impulse response (IIR) digital transmitter and receiver filters of class I is described. The filters are designed to be quasi-matched; each has a maximally flat delay polynomial as the denominator. Each filter is designed to have an equiripple stopband attenuation as well as low, uncontrolled intersymbol interference (ISI) when cascaded. In order to get low ISI and high stopband attenuation, it is necessary for the band-edge frequency to be slightly larger than the ideal value. A brief comparison with finite impulse response filter design is made. By IIR design, the filter order and group delay are reduced about 20% and 30% respectively, but the ISI is somewhat increased View full abstract»

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  • Simplified calculation of wave-coupling between lines in high-speed integrated circuits

    Publication Year: 1990 , Page(s): 1201 - 1208
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    The construction of time-domain solutions by the superposition of modes is explained for the general case, which may not have any symmetry in the lines or terminations. This simplified method requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of the actual logic gates. Several examples of results of crosstalk calculations made by the simplified method are presented and compared with corresponding results obtained using the SPICE transmission-line methods of Tripathi and Rettig (IEEE Trans. Microwave Theory Tech., vol. MTT-33, no.12, p.1513-18, 1985) along with full SPICE models of the logic gates. The simplified approach is shown to give satisfactory agreement for most purposes View full abstract»

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  • Switched-capacitor cascaded-biquad bandpass filters from MCPER functions

    Publication Year: 1990 , Page(s): 1304 - 1308
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    The multiple-critical-pole equiripple rational (MCPER) transfer functions are compared with the elliptic transfer functions in the design of bandpass switched-capacitor (SC) filters realized as a cascade of noninteracting biquads. Filters designed using the two classes of functions are investigated in terms of passband sensitivity, total capacitance, group delay, dynamic range, and noise. The results show that MCPER transfer functions allow the design of SC filters with superior performance, especially lower passband sensitivity View full abstract»

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  • Realizations of IIR/FIR and N-path filters using a novel switched-capacitor technique

    Publication Year: 1990 , Page(s): 1231 - 1247
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    Two canonical and two ladder structures are proposed for the realization of infinite impulse response (IIR) transfer functions using switched-capacitor (SC) differentiators and the synthetic division technique. The resultant filter structures are simple, compact, and stray insensitive. They have a low component sensitivity, good low-frequency noise performance, and adequate dynamic range. Theoretical calculation and SWITCAP simulation results on certain types of filters show good consistency with the experimental results, substantiating both design methodology and circuit functions. Circuit examples are given and their functions are successfully verified through chip fabrication and measurement. The multiplexed SC differentiators are modified to form three types of N-path circuits which can be used to design a narrowband bandpass filter. Because the N-path circuits are based upon SC differentiators rather than SC integrators, they have distinct performance superior to that of SC integrator-based N-path circuits View full abstract»

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  • Correction of capacitor errors during the conversion cycle of self-calibrating A/D converters

    Publication Year: 1990 , Page(s): 1296 - 1299
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    The conversion cycle of self-calibrating, successive approximation (analog/digital) A/D converters (ADCs) is analyzed. The effects of capacitor ratio mismatch errors on the transfer characteristics of unipolar and bipolar ADCs are presented. Error correction during conversion is shown to eliminate linearity errors in unipolar ADCs and offset and linearity errors in bipolar ADCs. It is shown that for bipolar ADCs, the correction algorithm depends on the way the average unit capacitor is defined, which essentially depends on the calibration algorithm used during the ADC calibration cycle. High-resolution ADC considerations are presented, and computer simulations are reported View full abstract»

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  • A parametric representation for k-variable Schur polynomials

    Publication Year: 1990 , Page(s): 1288 - 1291
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A parametric representation for k-variable polynomials with prescribed partial degrees is given, where the coefficients are functions of real parameter vectors. For these parameters, simple conditions which are sufficient to guarantee that the corresponding polynomials are widest-sense Schur are established. Simple necessary and sufficient conditions are introduced in the two-variable case so that the corresponding polynomials are scattering Schur. The synthesis of two-dimensional lossless one-ports and a parametric representation of constant unitary matrices form the basis of these considerations View full abstract»

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  • The pulse sorting transform

    Publication Year: 1990 , Page(s): 1193 - 1200
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    A modification of conventional Fourier transforms is presented. This modification is called the pulse sorting transform (PST) and is useful in extracting information from signals comprised of interleaved pulse trains. A brief derivation of the PST from the conventional transform is presented, followed by theorems that describe the PST's properties. Several examples of how the PST can be an effective tool in digital signal processing are presented. The examples demonstrate how the PST extracts phase information from interleaved pulse trains View full abstract»

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  • Complementary two-transistor circuits and negative differential resistance

    Publication Year: 1990 , Page(s): 1258 - 1266
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    The DC behavior of nonlinear one-ports using two complementary Ebers-Moll-modeled transistors and lacking internal independent sources is discussed. It is proven that, in the absence of internal resistors, all such one-ports-irrespective of their internal topology and transistor parameter values-cannot exhibit negative differential resistance (NDR) for any value of an external biasing current source. One circuit using two complementary transistors and no resistors is of particular interest, since it is often cited as a two-transistor simplified model for silicon-controlled rectifier devices. The results demonstrate that either the transistor behavior unaccounted for in an Ebers-Moll-type model must be involved in this one-port's NDR behavior, or the presence of internal resistors is essential to such a circuit's behavior having even a generally correct qualitative character View full abstract»

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  • A class of systolizable IIR digital filters and its design for proper scaling and minimum output roundoff noise

    Publication Year: 1990 , Page(s): 1217 - 1230
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB)  

    A class of infinite impulse response (IIR) digital filters with a systolizable structure is proposed and its synthesis is investigated. The systolizable structure consists of pipelineable regular modules with local connections and is suitable for VLSI implementation. It is capable of achieving high performance as well as high throughput. This class of filter structure provides certain degrees of freedom that can be used to obtain some desirable properties for the filter. Techniques of evaluating the internal signal powers and the output roundoff noise of the proposed filter structure are developed. Based upon these techniques, a well-scaled IIR digital filter with minimum output roundoff noise is designed with a local optimization approach. The internal signals of all the modes of this filter are scaled to unity in the l2-norm sense. Compared to the Rao-Kailath (1984) orthogonal digital filter and the Gray-Markel (1973) normalized-lattice digital filter, this filter has better scaling properties and lower output roundoff noise View full abstract»

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  • A multichannel minimum-seeking analog-to-digital converter

    Publication Year: 1990 , Page(s): 1314 - 1317
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    A special-purpose analog to digital (A/D) circuit using medium-scale integration ICs on a printed circuit board is developed. The circuit determines which of the eight input analog signals is the lowest and provides an 8-b magnitude and 3-b address output of this minimum input signal at a 0.5-MHz conversion rate. The circuit utilizes a successive approximation register, adder registers, CMOS D/A (digital/analog), parallel comparators, and a priority encoder connected in closed loop. Control is accomplished using simple flip-flop logic. Several important signal-processing applications are mentioned for this circuit as a feedback component in optical and electronic systems, utilizing associative self-organizing memory View full abstract»

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