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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 4 • Date April 2005

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2005 , Page(s): c1
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  • IEEE Transactions on Circuits and Systems–I: Regular Papers publication information

    Publication Year: 2005 , Page(s): c2
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  • Computation of period sensitivity functions for the simulation of phase noise in oscillators

    Publication Year: 2005 , Page(s): 681 - 694
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    Accurate phase noise simulation of circuits for radio frequency applications is of great importance during the design and development of wireless communication systems. In this paper, we present an approach based on the Floquet theory for the analysis and numerical computation of phase noise that solves some drawbacks implicitly present in previously proposed algorithms. In particular, we present an approach that computes the perturbation projection vector directly from the Jacobian matrix of the shooting method adopted to compute the steady-state solution. Further, we address some problems that arise when dealing with circuits whose modeling equations do not satisfy the Lipschitz condition at least from the numerical point of view. Frequency-domain aspects of phase noise analysis are also considered and, finally, simulation results for some benchmark circuits are presented. View full abstract»

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  • A micropower CMOS continuous-time filter with on-chip automatic tuning

    Publication Year: 2005 , Page(s): 695 - 705
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1568 KB) |  | HTML iconHTML  

    This paper presents a CMOS implementation of a low-voltage micropower Gm-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm2 excluding the area of the integrating capacitances. View full abstract»

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  • Behavioral analysis of self-oscillating class D line drivers

    Publication Year: 2005 , Page(s): 706 - 714
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    Self-oscillating power amplifiers (SOPAs) provide an elegant way to power signals which have high crest factors with a high efficiency. Recently, it has been shown that by pushing this concept to its limits, the stringent specifications of digital subscriber line (xDSL) could be met. For the design of these high bandwidth, low distortion amplifiers in a digital CMOS technology, a thorough analysis of the hard nonlinear system is mandatory. This paper describes behavioral models based on the describing function method and Bessel series expansion of nonlinear modulations. Models have been derived for the self-oscillation, the bandwidth, the dominant third-order distortion and all inter-modulation products of a SOPA line driver. All spectral peaks at the output of a single ended SOPA amplifier are qualitatively and quantitatively explained by these models with a very high accuracy. A calculation speed-up with three orders of magnitude could be obtained compared with a dedicated numerical simulator. View full abstract»

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  • Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators

    Publication Year: 2005 , Page(s): 715 - 722
    Cited by:  Papers (10)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    Double-sampling techniques allow to double the sampling frequency of a switched capacitor ΣΔ analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling ΣΔ modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling ΣΔ modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise. View full abstract»

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  • Event-driven Simulation and modeling of phase noise of an RF oscillator

    Publication Year: 2005 , Page(s): 723 - 733
    Cited by:  Papers (53)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process. View full abstract»

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  • A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

    Publication Year: 2005 , Page(s): 734 - 741
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes. View full abstract»

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  • Universal delay-insensitive systems with buffering lines

    Publication Year: 2005 , Page(s): 742 - 754
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata. View full abstract»

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  • Application-specific instruction set processor for SoC implementation of modern signal processing algorithms

    Publication Year: 2005 , Page(s): 755 - 765
    Cited by:  Papers (16)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. View full abstract»

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  • Block-LDPC: a practical LDPC coding system design approach

    Publication Year: 2005 , Page(s): 766 - 775
    Cited by:  Papers (85)  |  Patents (128)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    This paper presents a joint low-density parity-check (LDPC) code-encoder-decoder design approach, called Block-LDPC, for practical LDPC coding system implementations. The key idea is to construct LDPC codes subject to certain hardware-oriented constraints that ensure the effective encoder and decoder hardware implementations. We develop a set of hardware-oriented constraints, subject to which a semi-random approach is used to construct Block-LDPC codes with good error-correcting performance. Correspondingly, we develop an efficient encoding strategy and a pipelined partially parallel Block-LDPC encoder architecture, and a partially parallel Block-LDPC decoder architecture. We present the estimation of Block-LDPC coding system implementation key metrics including the throughput and hardware complexity for both encoder and decoder. The good error-correcting performance of Block-LDPC codes has been demonstrated through computer simulations. With the effective encoder/decoder design and good error-correcting performance, Block-LDPC provides a promising vehicle for real-life LDPC coding system implementations. View full abstract»

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  • A method for automatically finding multiple operating points in nonlinear circuits

    Publication Year: 2005 , Page(s): 776 - 784
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A new algorithm based on a SPICE-like simulator that searches for multiple operating points automatically, with no user intervention required, is presented. This algorithm, which exploits the asymmetrical properties of nonlinear mappings that describe multistable circuits, has been implemented into a program which automatically finds multiple (in most cases, all) operating points of a circuit. In addition to finding multiple operating points, this method offers another feature: it is capable of detecting the stability of a particular operating point. Another useful feature of this method is that it allows the user to gauge how close a particular circuit is to possessing multiple operating points. For circuits known to possess multiple operating points, this method allows the user to specify which operating point is encountered first. Unlike other continuation methods, circuit element models are not modified; only augmenting resistors are required. Hence, this approach lends itself well as an "add-on" to existing circuit simulators. A number of circuit examples are given. View full abstract»

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  • Efficiently searching the important input variables using Bayesian discriminant

    Publication Year: 2005 , Page(s): 785 - 793
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    This paper focuses on enhancing feature selection (FS) performance on a classification data set. First, a novel FS criterion using the concept of Bayesian discriminant is introduced. The proposed criterion is able to measure the classification ability of a feature set (or, a combination of the weighted features) in a direct way. This guarantees excellent FS results. Second, FS is conducted by optimizing the newly derived criterion in a continuous space instead of by heuristically searching features in a discrete feature space. Using this optimizing strategy, FS efficiency can be significantly improved. In this study, the proposed supervised FS scheme is compared with other related methods on different classification problems in which the number of features ranges from 33 to over 12,000. The presented results are very promising and corroborate the contributions of this study. View full abstract»

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  • Approximation of complex IIR bandpass filters without arithmetic symmetry

    Publication Year: 2005 , Page(s): 794 - 803
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    Complex transfer functions are not restricted to having complex-conjugate symmetry in the frequency-domain, as is the case for real filters. This gives them more flexibility when they are used in communication systems with complex signals, such as intermediate frequency signals of wireless communication systems. This paper describes a set of algorithms and procedures that can be used in solving the approximation problem involved in deriving complex infinite-impulse-response bandpass transfer functions directly, without the requirement of first designing a real-transfer-function prototype filter, which is then frequency translated. Because the requirement for a real prototype filter is eliminated, the filters need not have arithmetic symmetry; this results in superior stopbands with smaller filter orders. The procedures can be used for both continuous and discrete-time filters, can allow for arbitrary stopband specifications, and can be used for either equi-ripple or monotonic passbands. View full abstract»

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  • A critical analysis on global convergence of Hopfield-type neural networks

    Publication Year: 2005 , Page(s): 804 - 814
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB) |  | HTML iconHTML  

    This paper deals with the global convergence and stability of the Hopfield-type neural networks under the critical condition that M1(Γ)=L-1DΓ-(ΓW+WTΓ)/(2) is nonnegative for any diagonal matrix Γ, where W is the weight matrix of the network, L=diag{L1,L2,...,LN} with Li being the Lipschitz constant of gi and G(u)=(g1(u1),g2(u2),...,gN(uN))T is the activation mapping of the network. Many stability results have been obtained for the Hopfield-type neural networks in the noncritical case that M1(Γ) is positive definite for some positive definite diagonal matrix Γ. However, very few results are available on the global convergence and stability of the networks in the critical case. In this paper, by exploring two intrinsic features of the activation mapping, two generic global convergence results are established in the critical case for the Hopfield-type neural networks, which extend most of the previously known globally asymptotic stability criteria to the critical case. The results obtained discriminate the critical dynamics of the networks, and can be applied directly to a group of Hopfield-type neural network models. An example has also been presented to demonstrate both theoretical importance and practical significance of the critical results obtained. View full abstract»

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  • A compact f-f model of high-dimensional piecewise-linear function over a degenerate intersection

    Publication Year: 2005 , Page(s): 815 - 821
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    A novel f-f model is developed constructively which can express any n-dimensional piecewise linear (PWL) function by a superposition of basis functions if it is defined over an nth-order degenerate intersection formed by (n-1)th-order minimal degenerate intersections. We also propose the concrete functional forms of nth-order basis functions. Being the simplest type of the minimal degenerate intersection, the basis function is the most elementary "building block" of a PWL function defined in an arbitrary-dimensional space. In addition, the model constitutes a natural continuation to Julian's canonical formulation and can bridge the lattice PWL model and the well-established canonical representation. View full abstract»

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  • Correction to “Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter”

    Publication Year: 2005 , Page(s): 822
    Cited by:  Papers (1)
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  • The Fourth International Workshop on Multidimensional (nD) Systems NDS 2005

    Publication Year: 2005 , Page(s): 823
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    Freely Available from IEEE
  • Special issue on advances on life science systems and applications

    Publication Year: 2005 , Page(s): 824
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2005 , Page(s): c3
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2005 , Page(s): c4
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras